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Searched refs:mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h141 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h228 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h341 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_1_0_offset.h659 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h297 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h291 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h307 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h289 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … macro