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Searched refs:mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h49 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h138 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h225 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_1_0_offset.h497 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h179 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h163 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h165 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h147 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h689 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … macro