Searched refs:mmDAGB0_CNTL_MISC2_Sienna_Cichlid (Results 1 – 1 of 1) sorted by relevance
35 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070 macro575 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()609 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1); in mmhub_v2_0_update_medium_grain_clock_gating()687 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_get_clockgating()