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Searched refs:mmCP_RB_WPTR_POLL_ADDR_HI (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h522 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 macro
H A Dgfx_7_2_d.h219 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 macro
H A Dgfx_7_0_d.h219 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 macro
H A Dgfx_8_0_d.h243 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 macro
H A Dgfx_8_1_d.h244 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2386 #define mmCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_9_2_1_offset.h2601 #define mmCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_9_1_offset.h2663 #define mmCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_10_1_0_offset.h5031 #define mmCP_RB_WPTR_POLL_ADDR_HI macro
H A Dgc_10_3_0_offset.h4690 #define mmCP_RB_WPTR_POLL_ADDR_HI macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c6123 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, in gfx_v10_0_cp_gfx_resume()
6160 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, in gfx_v10_0_cp_gfx_resume()
H A Dgfx_v8_0.c4274 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3132 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()