Home
last modified time | relevance | path

Searched refs:mmCP_RB2_CNTL (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h507 #define mmCP_RB2_CNTL 0x3066 macro
H A Dgfx_7_2_d.h204 #define mmCP_RB2_CNTL 0x3066 macro
H A Dgfx_7_0_d.h204 #define mmCP_RB2_CNTL 0x3066 macro
H A Dgfx_8_0_d.h228 #define mmCP_RB2_CNTL 0x3066 macro
H A Dgfx_8_1_d.h229 #define mmCP_RB2_CNTL 0x3066 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2182 WREG32(mmCP_RB2_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2184 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2192 WREG32(mmCP_RB2_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2458 #define mmCP_RB2_CNTL … macro
H A Dgc_9_2_1_offset.h2673 #define mmCP_RB2_CNTL … macro
H A Dgc_9_1_offset.h2735 #define mmCP_RB2_CNTL … macro
H A Dgc_10_1_0_offset.h4801 #define mmCP_RB2_CNTL … macro
H A Dgc_10_3_0_offset.h4454 #define mmCP_RB2_CNTL … macro