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Searched refs:mmCP_RB0_BASE_HI (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h196 #define mmCP_RB0_BASE_HI 0x30b1 macro
H A Dgfx_7_0_d.h196 #define mmCP_RB0_BASE_HI 0x30b1 macro
H A Dgfx_8_0_d.h220 #define mmCP_RB0_BASE_HI 0x30b1 macro
H A Dgfx_8_1_d.h221 #define mmCP_RB0_BASE_HI 0x30b1 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2587 #define mmCP_RB0_BASE_HI … macro
H A Dgc_9_2_1_offset.h2791 #define mmCP_RB0_BASE_HI … macro
H A Dgc_9_1_offset.h2857 #define mmCP_RB0_BASE_HI … macro
H A Dgc_10_1_0_offset.h4927 #define mmCP_RB0_BASE_HI … macro
H A Dgc_10_3_0_offset.h4588 #define mmCP_RB0_BASE_HI … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2575 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v7_0_cp_gfx_resume()
H A Dgfx_v8_0.c4280 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3139 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v10_0.c6131 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v10_0_cp_gfx_resume()