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Searched refs:mmCP_HQD_HQ_CONTROL0 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_d.h666 #define mmCP_HQD_HQ_CONTROL0 0x3266 macro
H A Dgfx_8_0_d.h666 #define mmCP_HQD_HQ_CONTROL0 0x3266 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2887 #define mmCP_HQD_HQ_CONTROL0 … macro
H A Dgc_9_1_offset.h3115 #define mmCP_HQD_HQ_CONTROL0 … macro
H A Dgc_9_2_1_offset.h3071 #define mmCP_HQD_HQ_CONTROL0 … macro
H A Dgc_10_1_0_offset.h5369 #define mmCP_HQD_HQ_CONTROL0 … macro
H A Dgc_10_3_0_offset.h5004 #define mmCP_HQD_HQ_CONTROL0 … macro