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Searched refs:mmCP_CPC_IC_OP_CNTL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h349 #define mmCP_CPC_IC_OP_CNTL 0x30bc macro
H A Dgfx_8_1_d.h349 #define mmCP_CPC_IC_OP_CNTL 0x30bc macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c5583 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5585 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5589 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
6249 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_cp_compute_load_microcode()
6251 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
6255 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_cp_compute_load_microcode()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2609 #define mmCP_CPC_IC_OP_CNTL macro
H A Dgc_9_2_1_offset.h2813 #define mmCP_CPC_IC_OP_CNTL macro
H A Dgc_9_1_offset.h2879 #define mmCP_CPC_IC_OP_CNTL macro
H A Dgc_10_1_0_offset.h10283 #define mmCP_CPC_IC_OP_CNTL macro
H A Dgc_10_3_0_offset.h10005 #define mmCP_CPC_IC_OP_CNTL macro