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Searched refs:mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h1939 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h3156 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h3971 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_1_0_offset.h3953 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h3893 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h4512 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h4831 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h4559 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … macro