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Searched refs:mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h1390 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h2470 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h3281 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h3479 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h3321 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h3826 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h4259 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h3873 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … macro