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Searched refs:mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h1896 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h3094 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h3905 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h3827 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h4450 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h4765 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h4497 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro