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Searched refs:mmBL_PWM_PERIOD_CNTL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h5486 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h11366 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_1_0_offset.h10408 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h11446 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h12783 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h12594 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h1865 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro