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Searched refs:mmATC_L2_CACHE_4K_EDC_CNT (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c6549 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); in gfx_v9_0_query_utc_edc_status()
6606 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); in gfx_v9_0_query_utc_edc_status()
6702 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); in gfx_v9_0_reset_ras_error_count()
6721 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); in gfx_v9_0_reset_ras_error_count()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1158 #define mmATC_L2_CACHE_4K_EDC_CNT macro