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Searched refs:mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h6883 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h11603 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_1_0_offset.h5588 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h14247 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h15847 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro