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Searched refs:misc1 (Results 1 – 16 of 16) sorted by relevance

/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc227 XTREG(103, 412, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1,
H A Dxtensa-modules.c.inc11392 { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
11395 { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
11398 { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
12449 return 215; /* xsr.misc1 */
12649 return 213; /* rsr.misc1 */
12784 return 214; /* wsr.misc1 */
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc112 XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc9234 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
9237 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
9240 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc129 XTREG(104, 416, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc12038 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
12041 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
12044 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dimx-regs.h326 u32 misc1; member
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc125 XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc27275 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
27278 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
27281 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc121 XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11407 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
11410 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
11413 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc158 XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc33551 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
33554 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
33557 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc162 XTREG(123,556,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16660 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
16663 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
16666 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc8265 { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */,
8268 { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */,
8271 { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */,
8908 return 186; /* xsr.misc1 */
9055 return 184; /* rsr.misc1 */
9152 return 185; /* wsr.misc1 */