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Searched refs:misa_mxl (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu.h171 uint32_t misa_mxl; /* current mxl */ member
563 return env->misa_mxl;
586 RISCVMXL xl = env->misa_mxl; in cpu_get_xl()
617 return env->misa_mxl; in cpu_recompute_xl()
648 return env->misa_mxl; in riscv_cpu_sxl()
H A Dcpu.c279 env->misa_mxl_max = env->misa_mxl = mxl; in riscv_cpu_set_misa()
848 env->misa_mxl = env->misa_mxl_max; in riscv_cpu_reset_hold()
851 if (env->misa_mxl > MXL_RV32) { in riscv_cpu_reset_hold()
856 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold()
857 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold()
860 MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold()
862 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold()
864 MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold()
866 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold()
1126 if (cpu->env.misa_mxl == MXL_RV32) { in riscv_add_satp_mode_properties()
H A Dmachine.c373 VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
H A Dcsr.c1400 switch (env->misa_mxl) { in read_misa()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c172 if (env->misa_mxl_max != env->misa_mxl) { in riscv_cpu_validate_misa_mxl()
968 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
987 if (env->misa_mxl != MXL_RV32) { in riscv_init_max_cpu_extensions()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c1507 env->misa_mxl_max = env->misa_mxl = MXL_RV32; in riscv_host_cpu_init()
1509 env->misa_mxl_max = env->misa_mxl = MXL_RV64; in riscv_host_cpu_init()