Searched refs:misa_mxl (Results 1 – 6 of 6) sorted by relevance
/openbmc/qemu/target/riscv/ |
H A D | cpu.h | 171 uint32_t misa_mxl; /* current mxl */ member 563 return env->misa_mxl; 586 RISCVMXL xl = env->misa_mxl; in cpu_get_xl() 617 return env->misa_mxl; in cpu_recompute_xl() 648 return env->misa_mxl; in riscv_cpu_sxl()
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H A D | cpu.c | 279 env->misa_mxl_max = env->misa_mxl = mxl; in riscv_cpu_set_misa() 848 env->misa_mxl = env->misa_mxl_max; in riscv_cpu_reset_hold() 851 if (env->misa_mxl > MXL_RV32) { in riscv_cpu_reset_hold() 856 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold() 857 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold() 860 MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold() 862 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold() 864 MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold() 866 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold() 1126 if (cpu->env.misa_mxl == MXL_RV32) { in riscv_add_satp_mode_properties()
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H A D | machine.c | 373 VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
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H A D | csr.c | 1400 switch (env->misa_mxl) { in read_misa()
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/openbmc/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 172 if (env->misa_mxl_max != env->misa_mxl) { in riscv_cpu_validate_misa_mxl() 968 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions() 987 if (env->misa_mxl != MXL_RV32) { in riscv_init_max_cpu_extensions()
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/openbmc/qemu/target/riscv/kvm/ |
H A D | kvm-cpu.c | 1507 env->misa_mxl_max = env->misa_mxl = MXL_RV32; in riscv_host_cpu_init() 1509 env->misa_mxl_max = env->misa_mxl = MXL_RV64; in riscv_host_cpu_init()
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