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Searched refs:misa_ext_mask (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c309 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
756 env->misa_ext_mask |= misa_bit; in cpu_set_misa_ext_cfg()
759 env->misa_ext_mask &= ~misa_bit; in cpu_set_misa_ext_cfg()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c151 bool value = env->misa_ext_mask & misa_bit; in kvm_cpu_get_misa_ext_cfg()
170 host_bit = env->misa_ext_mask & misa_bit; in kvm_cpu_set_misa_ext_cfg()
783 reg.addr = (uint64_t)&env->misa_ext_mask; in kvm_riscv_init_misa_ext_mask()
793 env->misa_ext = env->misa_ext_mask; in kvm_riscv_init_misa_ext_mask()
/openbmc/qemu/target/riscv/
H A Dmachine.c376 VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
H A Dcpu.h174 uint32_t misa_ext_mask; /* max ext for this cpu */ member
H A Dcpu.c280 env->misa_ext_mask = env->misa_ext = ext; in riscv_cpu_set_misa()
H A Dcsr.c1430 val &= env->misa_ext_mask; in write_misa()