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Searched refs:miig_rt (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_classifier.c212 regmap_write(miig_rt, offset, val); in rx_class_ft1_set_start_len()
265 regmap_write(miig_rt, offset, data); in rx_class_set_and()
274 regmap_write(miig_rt, offset, data); in rx_class_set_or()
303 rx_class_set_and(miig_rt, slice, n, 0); in icssg_class_disable()
305 rx_class_set_or(miig_rt, slice, n, 0); in icssg_class_disable()
312 regmap_read(miig_rt, offset, &data); in icssg_class_disable()
317 regmap_write(miig_rt, offset, data); in icssg_class_disable()
324 rx_class_ft1_cfg_set_type(miig_rt, slice, n, in icssg_class_disable()
326 rx_class_ft1_set_da(miig_rt, slice, n, addr); in icssg_class_disable()
339 icssg_class_disable(miig_rt, slice); in icssg_class_default()
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H A Dicssg_mii_cfg.c44 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac) in icssg_update_rgmii_cfg() argument
54 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val); in icssg_update_rgmii_cfg()
60 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val); in icssg_update_rgmii_cfg()
66 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask, in icssg_update_rgmii_cfg()
82 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); in icssg_miig_set_interface_mode()
83 regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val); in icssg_miig_set_interface_mode()
90 regmap_read(miig_rt, RGMII_CFG_OFFSET, &val); in icssg_rgmii_cfg_get_bitfield()
97 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii) in icssg_rgmii_get_speed() argument
106 return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift); in icssg_rgmii_get_speed()
109 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii) in icssg_rgmii_get_fullduplex() argument
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H A Dicssg_queues.c23 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt); in icssg_queue_pop()
27 regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val); in icssg_queue_pop()
37 regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr); in icssg_queue_push()
47 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &reg); in icssg_queue_level()
H A Dicssg_config.c145 struct regmap *miig_rt = prueth->miig_rt; in icssg_miig_queues_init() local
156 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
161 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
164 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, in icssg_miig_queues_init()
195 regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, in icssg_miig_queues_init()
321 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, in icssg_init_emac_mode()
323 regmap_write(prueth->miig_rt, FDB_GEN_CFG2, 0); in icssg_init_emac_mode()
325 icssg_class_set_host_mac_addr(prueth->miig_rt, mac); in icssg_init_emac_mode()
345 regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET, in icssg_config()
347 icssg_miig_set_interface_mode(prueth->miig_rt, slice, emac->phy_if); in icssg_config()
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H A Dicssg_mii_rt.h145 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac);
146 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift);
147 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii);
148 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii);
149 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if);
H A Dicssg_prueth.h226 struct regmap *miig_rt; member
273 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
274 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);
275 void icssg_class_disable(struct regmap *miig_rt, int slice);
276 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti);
277 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
H A Dicssg_stats.c29 regmap_read(prueth->miig_rt, in emac_update_hardware_stats()
32 regmap_write(prueth->miig_rt, in emac_update_hardware_stats()
H A Dicssg_prueth.c1036 icssg_update_rgmii_cfg(prueth->miig_rt, emac); in emac_adjust_link()
1334 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); in emac_ndo_open()
1335 icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); in emac_ndo_open()
1337 icssg_class_default(prueth->miig_rt, slice, 0); in emac_ndo_open()
1466 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); in emac_ndo_stop()
2026 prueth->miig_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-g-rt"); in prueth_probe()
2027 if (IS_ERR(prueth->miig_rt)) { in prueth_probe()