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Searched refs:miclaim (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmachine.c417 VMSTATE_UINT64(env.miclaim, RISCVCPU),
H A Dcpu.h278 uint64_t miclaim; member
H A Dcpu_helper.c705 if (env->miclaim & interrupts) { in riscv_cpu_claim_interrupts()
708 env->miclaim |= interrupts; in riscv_cpu_claim_interrupts()
H A Dcpu.c964 env->miclaim = MIP_SGEIP; in riscv_cpu_reset_hold()