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Searched refs:mhpmeventh_val (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c112 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || in riscv_pmu_incr_ctr_rv32()
114 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || in riscv_pmu_incr_ctr_rv32()
116 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || in riscv_pmu_incr_ctr_rv32()
118 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || in riscv_pmu_incr_ctr_rv32()
120 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { in riscv_pmu_incr_ctr_rv32()
130 if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { in riscv_pmu_incr_ctr_rv32()
131 env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF; in riscv_pmu_incr_ctr_rv32()
350 mhpmevent_val = &env->mhpmeventh_val[ctr_idx]; in pmu_timer_trigger_irq()
H A Dmachine.c407 VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
H A Dcpu.h329 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; member
H A Dcsr.c830 ((uint64_t)env->mhpmeventh_val[evt_index] << 32); in write_mhpmevent()
841 *val = env->mhpmeventh_val[evt_index]; in read_mhpmeventh()
853 env->mhpmeventh_val[evt_index] = val; in write_mhpmeventh()
984 mhpm_evt_val = env->mhpmeventh_val; in read_scountovf()