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Searched refs:mhpmevent_val (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c153 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || in riscv_pmu_incr_ctr_rv64()
155 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || in riscv_pmu_incr_ctr_rv64()
157 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || in riscv_pmu_incr_ctr_rv64()
159 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || in riscv_pmu_incr_ctr_rv64()
161 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { in riscv_pmu_incr_ctr_rv64()
170 env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF; in riscv_pmu_incr_ctr_rv64()
334 target_ulong *mhpmevent_val; in pmu_timer_trigger_irq() local
350 mhpmevent_val = &env->mhpmeventh_val[ctr_idx]; in pmu_timer_trigger_irq()
353 mhpmevent_val = &env->mhpmevent_val[ctr_idx]; in pmu_timer_trigger_irq()
368 if (!(*mhpmevent_val & of_bit_mask)) { in pmu_timer_trigger_irq()
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H A Dmachine.c406 VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
H A Dcpu.h326 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; member
H A Dcsr.c816 *val = env->mhpmevent_val[evt_index]; in read_mhpmevent()
826 env->mhpmevent_val[evt_index] = val; in write_mhpmevent()
850 uint64_t mhpmevt_val = env->mhpmevent_val[evt_index]; in write_mhpmeventh()
987 mhpm_evt_val = env->mhpmevent_val; in read_scountovf()