Searched refs:memory_width (Results 1 – 4 of 4) sorted by relevance
49 int memory_width; member123 fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */ in nv10_calc_arb()150 * arb->memory_width / 32; in nv10_calc_arb()219 sim_data.memory_width = 64; in nv04_update_arb()224 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; in nv04_update_arb()
193 int memory_width; member214 int memory_width; member235 int memory_width; member437 eburst_size = state->memory_width * 1; in nv3_arb()629 sim_data.memory_width = 128; in nv3UpdateArbitrationSettings()671 width = arb->memory_width >> 6; in nv4CalcArbitration()857 width = arb->memory_width/64; in nv10CalcArbitration()881 if (arb->memory_width == 64) /* 64 bit bus */ in nv10CalcArbitration()886 if (arb->memory_width == 64) /* 64 bit bus */ in nv10CalcArbitration()891 if ((!video_enable) && (arb->memory_width == 128)) in nv10CalcArbitration()[all …]
111 u8 memory_width; member181 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()191 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()
110 int memory_width; member133 int memory_width; member257 width = arb->memory_width >> 6; in nv4CalcArbitration()395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv4UpdateArbitrationSettings()435 width = arb->memory_width / 64; in nv10CalcArbitration()458 if (arb->memory_width == 64) /* 64 bit bus */ in nv10CalcArbitration()462 else if (arb->memory_width == 64) /* 64 bit bus */ in nv10CalcArbitration()467 if ((!video_enable) && (arb->memory_width == 128)) { in nv10CalcArbitration()635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv10UpdateArbitrationSettings()715 sim_data.memory_width = 64; in nForceUpdateArbitrationSettings()