| /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | cpu_init.c | 23 memctl8xx_t __iomem *memctl = &immr->im_memctl; in cpu_init_f() local
101 clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V); in cpu_init_f()
128 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP); in cpu_init_f()
131 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP); in cpu_init_f()
134 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP); in cpu_init_f()
138 out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM); in cpu_init_f()
139 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM); in cpu_init_f()
142 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); in cpu_init_f()
143 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); in cpu_init_f()
147 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM); in cpu_init_f()
[all …]
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| H A D | cpu.c | 106 memctl8xx_t __iomem *memctl = &immap->im_memctl; in checkicache() local
109 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; in checkicache()
147 memctl8xx_t __iomem *memctl = &immap->im_memctl; in checkdcache() local
150 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; in checkdcache()
183 memctl8xx_t __iomem *memctl = &immap->im_memctl; in upmconfig() local
186 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */ in upmconfig()
187 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */ in upmconfig()
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| H A D | immap.c | 42 memctl8xx_t __iomem *memctl = &immap->im_memctl; in do_memcinfo() local
44 uint __iomem *p = &memctl->memc_br0; in do_memcinfo()
51 printf("MAR = %08x", in_be32(&memctl->memc_mar)); in do_memcinfo()
52 printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr)); in do_memcinfo()
54 in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr)); in do_memcinfo()
55 printf("\nMSTAT = %04x\n", in_be16(&memctl->memc_mstat)); in do_memcinfo()
57 in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr)); in do_memcinfo()
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| /openbmc/u-boot/board/cssi/MCR3000/ |
| H A D | MCR3000.c | 93 memctl8xx_t __iomem *memctl = &immap->im_memctl; in dram_init() local
101 out_be16(&memctl->memc_mptpr, 0x0200); in dram_init()
102 out_be32(&memctl->memc_mamr, 0x14904000); in dram_init()
104 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); in dram_init()
105 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); in dram_init()
107 out_be32(&memctl->memc_mcr, 0x80002830); in dram_init()
108 out_be32(&memctl->memc_mar, 0x00000088); in dram_init()
109 out_be32(&memctl->memc_mcr, 0x80002038); in dram_init()
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| /openbmc/linux/drivers/gpu/drm/mgag200/ |
| H A D | mgag200_g200er.c | 42 u32 memctl; in mgag200_g200er_reset_tagfifo() local
44 memctl = RREG32(MGAREG_MEMCTL); in mgag200_g200er_reset_tagfifo()
46 memctl |= RESET_FLAG; in mgag200_g200er_reset_tagfifo()
47 WREG32(MGAREG_MEMCTL, memctl); in mgag200_g200er_reset_tagfifo()
51 memctl &= ~RESET_FLAG; in mgag200_g200er_reset_tagfifo()
52 WREG32(MGAREG_MEMCTL, memctl); in mgag200_g200er_reset_tagfifo()
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| /openbmc/u-boot/drivers/usb/host/ |
| H A D | sl811-hcd.c | 95 volatile memctl8xx_t *memctl = &immap->im_memctl; in usb_init_kup4x() local
99 memctl = &immap->im_memctl; in usb_init_kup4x()
100 memctl->memc_or7 = 0xFFFF8726; in usb_init_kup4x()
101 memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ in usb_init_kup4x()
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| /openbmc/linux/arch/mips/boot/dts/ralink/ |
| H A D | mt7621.dtsi | 67 ralink,memctl = <&memc>;
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| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | xtensa-modules.c.inc | 8982 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
8985 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
8988 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
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| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | xtensa-modules.c.inc | 11155 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
11158 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
11161 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | xtensa-modules.c.inc | 16417 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
16420 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
16423 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
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| /openbmc/qemu/target/xtensa/ |
| H A D | translate.c | 2698 gen_translate_xsr(memctl)
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| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | xtensa-modules.c.inc | 33296 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
33299 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
33302 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
|