/openbmc/linux/drivers/gpu/drm/msm/disp/mdp4/ |
H A D | mdp4_lcdc_encoder.c | 80 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy() 205 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30); in setup_phy() 249 mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL, in mdp4_lcdc_encoder_mode_set() 254 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL, in mdp4_lcdc_encoder_mode_set() 259 mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0); in mdp4_lcdc_encoder_mode_set() 260 mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR, in mdp4_lcdc_encoder_mode_set() 265 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL, in mdp4_lcdc_encoder_mode_set() 268 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0); in mdp4_lcdc_encoder_mode_set() 269 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0); in mdp4_lcdc_encoder_mode_set() 284 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); in mdp4_lcdc_encoder_disable() [all …]
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H A D | mdp4_dsi_encoder.c | 71 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, in mdp4_dsi_encoder_mode_set() 75 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len); in mdp4_dsi_encoder_mode_set() 76 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, in mdp4_dsi_encoder_mode_set() 82 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); in mdp4_dsi_encoder_mode_set() 83 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, in mdp4_dsi_encoder_mode_set() 86 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL, in mdp4_dsi_encoder_mode_set() 90 mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0); in mdp4_dsi_encoder_mode_set() 91 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VSTART, 0); in mdp4_dsi_encoder_mode_set() 92 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0); in mdp4_dsi_encoder_mode_set() 103 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); in mdp4_dsi_encoder_disable() [all …]
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H A D | mdp4_dtv_encoder.c | 74 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set() 78 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set() 79 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set() 84 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set() 85 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set() 89 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); in mdp4_dtv_encoder_mode_set() 90 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, in mdp4_dtv_encoder_mode_set() 93 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0); in mdp4_dtv_encoder_mode_set() 94 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); in mdp4_dtv_encoder_mode_set() 105 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); in mdp4_dtv_encoder_disable() [all …]
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H A D | mdp4_crtc.c | 94 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); in crtc_flush() 241 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma), in mdp4_crtc_mode_set_nofb() 246 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0); in mdp4_crtc_mode_set_nofb() 248 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma), in mdp4_crtc_mode_set_nofb() 252 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0); in mdp4_crtc_mode_set_nofb() 253 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp), in mdp4_crtc_mode_set_nofb() 256 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0); in mdp4_crtc_mode_set_nofb() 258 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1); in mdp4_crtc_mode_set_nofb() 384 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), in update_cursor() 393 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), in update_cursor() [all …]
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H A D | mdp4_plane.c | 171 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), in mdp4_plane_set_scanout() 173 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe), in mdp4_plane_set_scanout() 175 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe), in mdp4_plane_set_scanout() 177 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe), in mdp4_plane_set_scanout() 187 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i), in mdp4_write_csc_config() 299 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe), in mdp4_plane_mode_set() 303 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe), in mdp4_plane_mode_set() 307 mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe), in mdp4_plane_mode_set() 311 mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe), in mdp4_plane_mode_set() 317 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe), in mdp4_plane_mode_set() [all …]
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H A D | mdp4_kms.c | 30 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); in mdp4_hw_init() 33 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); in mdp4_hw_init() 57 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); in mdp4_hw_init() 60 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); in mdp4_hw_init() 61 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); in mdp4_hw_init() 62 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); in mdp4_hw_init() 63 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); in mdp4_hw_init() 68 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); in mdp4_hw_init() 490 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); in mdp4_kms_init() 491 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); in mdp4_kms_init() [all …]
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H A D | mdp4_irq.c | 16 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_CLEAR, in mdp4_set_irqmask() 18 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); in mdp4_set_irqmask() 39 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall() 40 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_preinstall() 63 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_uninstall() 77 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); in mdp4_irq()
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H A D | mdp4_lvds_pll.c | 69 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable() 72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable() 74 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable() 90 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable() 91 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
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H A D | mdp4_kms.h | 45 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() function
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