Searched refs:mdc_divisor (Results 1 – 1 of 1) sorted by relevance
174 u8 mdc_divisor; member549 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9)); in ep93xx_start_hw()553 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8)); in ep93xx_start_hw()841 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */ in ep93xx_eth_probe()