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Searched refs:mcyclecfgh (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu.h375 target_ulong mcyclecfgh; member
H A Dcsr.c862 *val = env->mcyclecfgh; in read_mcyclecfgh()
880 env->mcyclecfgh = val & inh_avail_mask; in write_mcyclecfgh()
1020 cfg_val = upper_half ? ((uint64_t)env->mcyclecfgh << 32) : in riscv_pmu_ctr_get_fixed_counters_val()