Searched refs:mctrl (Results 1 – 8 of 8) sorted by relevance
| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | cpu.c | 31 | WDTIM_MCTRL_M_RES2, &wdt->mctrl); in reset_cpu()
37 writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); in reset_cpu()
|
| /openbmc/u-boot/board/work-microwave/work_92105/ |
| H A D | work_92105.c | 28 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()
30 writel(0, &wdt->mctrl); in reset_periph()
|
| /openbmc/u-boot/board/timll/devkit3250/ |
| H A D | devkit3250.c | 26 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()
29 writel(0, &wdt->mctrl); in reset_periph()
|
| /openbmc/qemu/hw/misc/ |
| H A D | slavio_misc.c | 60 uint8_t diag, mctrl; member
110 s->config = s->aux1 = s->aux2 = s->mctrl = 0; in slavio_misc_reset()
193 s->mctrl = val & 0xff; in slavio_mdm_mem_writeb()
202 ret = s->mctrl; in slavio_mdm_mem_readb()
417 VMSTATE_UINT8(mctrl, MiscState),
|
| /openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | wdt.h | 16 u32 mctrl; /* Match Control Register */ member
|
| /openbmc/u-boot/arch/arm/mach-zynq/ |
| H A D | cpu.c | 75 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) in zynq_get_silicon_version()
|
| /openbmc/u-boot/arch/arm/mach-zynq/include/mach/ |
| H A D | hardware.h | 107 u32 mctrl; /* 0x80 */ member
|
| /openbmc/u-boot/drivers/fpga/ |
| H A D | zynqpl.c | 201 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); in zynq_dma_xfer_init()
262 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); in zynq_dma_xfer_init()
|