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Searched refs:mcr (Results 1 – 25 of 238) sorted by relevance

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/openbmc/linux/arch/arm/mm/
H A Dproc-arm940.S280 mcr p15, 0, r0, c6, c4, 0
281 mcr p15, 0, r0, c6, c5, 0
282 mcr p15, 0, r0, c6, c6, 0
283 mcr p15, 0, r0, c6, c7, 0
286 mcr p15, 0, r0, c6, c4, 1
287 mcr p15, 0, r0, c6, c5, 1
288 mcr p15, 0, r0, c6, c6, 1
289 mcr p15, 0, r0, c6, c7, 1
293 mcr p15, 0, r0, c6, c0, 1
299 mcr p15, 0, r3, c6, c1, 1
[all …]
H A Dproc-mohawk.S63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
182 mcr p15, 0, r0, c7, c10, 4 @ drain WB
203 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 mcr p15, 0, r0, c7, c10, 4 @ drain WB
248 mcr p15, 0, r0, c7, c10, 4 @ drain WB
266 mcr p15, 0, r0, c7, c10, 4 @ drain WB
304 mcr p15, 0, r0, c7, c10, 4 @ drain WB
319 mcr p15, 0, ip, c7, c10, 4 @ drain WB
336 mcr p15, 0, r0, c7, c10, 4 @ drain WB
365 mcr p15, 0, r6, c13, c0, 0 @ PID
[all …]
H A Dproc-arm946.S59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
188 mcr p15, 0, r0, c7, c10, 4 @ drain WB
210 mcr p15, 0, r0, c7, c10, 4 @ drain WB
237 mcr p15, 0, r0, c7, c10, 4 @ drain WB
333 mcr p15, 0, r0, c6, c4, 0
334 mcr p15, 0, r0, c6, c5, 0
335 mcr p15, 0, r0, c6, c6, 0
336 mcr p15, 0, r0, c6, c7, 0
344 mcr p15, 0, r3, c6, c1, 0
349 mcr p15, 0, r3, c6, c2, 0
[all …]
H A Dproc-fa526.S39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
127 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
129 mcr p15, 0, r0, c7, c10, 4 @ drain WB
145 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
[all …]
H A Dproc-arm1020.S86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
175 mcr p15, 0, ip, c7, c10, 4
177 mcr p15, 0, ip, c7, c10, 4 @ drain WB
215 mcr p15, 0, ip, c7, c10, 4
219 mcr p15, 0, ip, c7, c10, 4 @ drain WB
321 mcr p15, 0, ip, c7, c10, 4
386 mcr p15, 0, r3, c7, c10, 4
393 mcr p15, 0, ip, c7, c10, 4
[all …]
H A Dproc-arm926.S70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
209 mcr p15, 0, r0, c7, c10, 4 @ drain WB
230 mcr p15, 0, r0, c7, c10, 4 @ drain WB
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
301 mcr p15, 0, r0, c7, c10, 4 @ drain WB
341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
365 mcr p15, 0, ip, c7, c10, 4 @ drain WB
406 mcr p15, 0, r4, c13, c0, 0 @ PID
407 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
[all …]
H A Dproc-arm925.S110 mcr p15, 0, ip, c7, c10, 4 @ drain WB
117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
267 mcr p15, 0, r0, c7, c10, 4 @ drain WB
295 mcr p15, 0, r0, c7, c10, 4 @ drain WB
316 mcr p15, 0, r0, c7, c10, 4 @ drain WB
338 mcr p15, 0, r0, c7, c10, 4 @ drain WB
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB
404 mcr p15, 0, ip, c7, c10, 4 @ drain WB
423 mcr p15, 0, r0, c7, c10, 4 @ drain WB
[all …]
H A Dproc-arm920.S61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
198 mcr p15, 0, r0, c7, c10, 4 @ drain WB
219 mcr p15, 0, r0, c7, c10, 4 @ drain WB
245 mcr p15, 0, r0, c7, c10, 4 @ drain WB
264 mcr p15, 0, r0, c7, c10, 4 @ drain WB
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
352 mcr p15, 0, ip, c7, c10, 4 @ drain WB
369 mcr p15, 0, r0, c7, c10, 4 @ drain WB
391 mcr p15, 0, r4, c13, c0, 0 @ PID
[all …]
H A Dproc-sa1100.S57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB
185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
187 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
190 mcr p15, 0, r4, c3, c0, 0 @ domain ID
[all …]
H A Dproc-v6.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
63 mcr p15, 0, r1, c7, c5, 4 @ ISB
104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 mcr p15, 0, r1, c13, c0, 1 @ set context ID
161 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
163 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
172 mcr p15, 0, ip, c7, c5, 4 @ ISB
202 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
[all …]
H A Dproc-arm922.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
200 mcr p15, 0, r0, c7, c10, 4 @ drain WB
221 mcr p15, 0, r0, c7, c10, 4 @ drain WB
247 mcr p15, 0, r0, c7, c10, 4 @ drain WB
266 mcr p15, 0, r0, c7, c10, 4 @ drain WB
283 mcr p15, 0, r0, c7, c10, 4 @ drain WB
356 mcr p15, 0, ip, c7, c10, 4 @ drain WB
372 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
H A Dproc-feroceon.S72 mcr p15, 1, r0, c15, c9, 0 @ clean L2
73 mcr p15, 0, r0, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c7, c10, 4 @ drain WB
225 mcr p15, 0, r0, c7, c10, 4 @ drain WB
247 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
288 mcr p15, 0, r0, c7, c10, 4 @ drain WB
324 mcr p15, 0, r0, c7, c10, 4 @ drain WB
337 mcr p15, 0, r0, c7, c10, 4 @ drain WB
526 mcr p15, 0, r4, c13, c0, 0 @ PID
[all …]
H A Dproc-arm1020e.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
221 mcr p15, 0, ip, c7, c10, 4 @ drain WB
243 mcr p15, 0, ip, c7, c10, 4 @ drain WB
272 mcr p15, 0, ip, c7, c10, 4 @ drain WB
294 mcr p15, 0, ip, c7, c10, 4 @ drain WB
314 mcr p15, 0, ip, c7, c10, 4 @ drain WB
371 mcr p15, 0, r3, c7, c10, 4
[all …]
H A Dcache-v6.S51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
188 mcr p15, 0, r0, c7, c10, 4
228 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
240 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
255 mcr p15, 0, r0, c7, c10, 1 @ clean D line
257 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
[all …]
H A Dproc-xscale.S118 mcr p15, 0, r1, c1, c0, 1
128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
154 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
179 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
290 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
549 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
550 mcr p15, 0, r6, c13, c0, 0 @ PID
[all …]
H A Dproc-xsc3.S92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
364 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
435 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
436 mcr p15, 0, r6, c13, c0, 0 @ PID
437 mcr p15, 0, r7, c3, c0, 0 @ domain ID
[all …]
H A Dproc-arm1022.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
213 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 mcr p15, 0, ip, c7, c10, 4 @ drain WB
243 mcr p15, 0, ip, c7, c10, 4 @ drain WB
272 mcr p15, 0, ip, c7, c10, 4 @ drain WB
294 mcr p15, 0, ip, c7, c10, 4 @ drain WB
314 mcr p15, 0, ip, c7, c10, 4 @ drain WB
383 mcr p15, 0, r1, c7, c10, 4 @ drain WB
[all …]
H A Dproc-arm1026.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
207 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
215 mcr p15, 0, ip, c7, c10, 4 @ drain WB
237 mcr p15, 0, ip, c7, c10, 4 @ drain WB
266 mcr p15, 0, ip, c7, c10, 4 @ drain WB
288 mcr p15, 0, ip, c7, c10, 4 @ drain WB
308 mcr p15, 0, ip, c7, c10, 4 @ drain WB
372 mcr p15, 0, r1, c7, c10, 4 @ drain WB
[all …]
H A Dproc-sa110.S37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
154 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
H A Dcache-fa.S44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
133 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
154 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
180 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
H A Dproc-arm740.S40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
67 mcr p15, 0, r0, c6, c6
68 mcr p15, 0, r0, c6, c7
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
[all …]
H A Dtlb-v6.S39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
85 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dstart.S111 mcr p15, 0, r0, c1, c0, 0
131 mcr p15, 0, r0, c3, c0, 0
135 mcr p15, 0, r0, c2, c0, 0
143 mcr p15, 0, r0, c1, c0, 0
147 mcr p15, 0, r0, c9, c1, 1
148 mcr p15, 0, r0, c9, c2, 1
151 mcr p15, 0, r0, c7, c7, 0
158 mcr p15, 0, r0, c8, c7, 0
168 mcr p15, 0, r0, c9, c2, 0
176 mcr p15, 0, r1, c7, c2, 5
[all …]
/openbmc/linux/drivers/w1/masters/
H A Dsgi_w1.c23 u32 __iomem *mcr; member
28 static u8 sgi_w1_wait(u32 __iomem *mcr) in sgi_w1_wait() argument
33 mcr_val = readl(mcr); in sgi_w1_wait()
49 writel(MCR_PACK(520, 65), dev->mcr); in sgi_w1_reset_bus()
50 ret = sgi_w1_wait(dev->mcr); in sgi_w1_reset_bus()
66 writel(MCR_PACK(6, 13), dev->mcr); in sgi_w1_touch_bit()
68 writel(MCR_PACK(80, 30), dev->mcr); in sgi_w1_touch_bit()
70 ret = sgi_w1_wait(dev->mcr); in sgi_w1_touch_bit()
86 sdev->mcr = devm_platform_ioremap_resource(pdev, 0); in sgi_w1_probe()
87 if (IS_ERR(sdev->mcr)) in sgi_w1_probe()
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dimx93_adc.c104 u32 mcr, msr; in imx93_adc_power_down() local
107 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_power_down()
109 writel(mcr, adc->regs + IMX93_ADC_MCR); in imx93_adc_power_down()
123 u32 mcr; in imx93_adc_power_up() local
126 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_power_up()
128 writel(mcr, adc->regs + IMX93_ADC_MCR); in imx93_adc_power_up()
133 u32 mcr; in imx93_adc_config_ad_clk() local
139 mcr = readl(adc->regs + IMX93_ADC_MCR); in imx93_adc_config_ad_clk()
141 writel(mcr, adc->regs + IMX93_ADC_MCR); in imx93_adc_config_ad_clk()
148 u32 mcr, msr; in imx93_adc_calibration() local
[all …]

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