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Searched refs:mcause (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/tests/tcg/riscv64/
H A Dtest-mepc-masking.S36 csrr t0, mcause
/openbmc/qemu/target/riscv/
H A Dmachine.c446 VMSTATE_UINTTL(env.mcause, RISCVCPU),
H A Dcpu_helper.c2432 env->mcause = cause | ((target_ulong)async << (mxlen - 1)); in riscv_cpu_do_interrupt()
2434 env->mtval2 = env->mcause; in riscv_cpu_do_interrupt()
2435 env->mcause = RISCV_EXCP_DOUBLE_TRAP; in riscv_cpu_do_interrupt()
H A Dcpu.h326 target_ulong mcause; member
H A Dcpu.c722 env->mcause = 0; in riscv_cpu_reset_hold()
H A Dcsr.c3152 *val = env->mcause; in read_mcause()
3159 env->mcause = val; in write_mcause()