Home
last modified time | relevance | path

Searched refs:main_pll_pllc0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h45 u32 main_pll_pllc0; member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c74 writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); in cm_basic_init()