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Searched refs:lpddr3_ctrl_phy_reset (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init.h98 unsigned lpddr3_ctrl_phy_reset; member
H A Dclock_init_exynos5.c201 .lpddr3_ctrl_phy_reset = 0x1,
304 .lpddr3_ctrl_phy_reset = 0x1,
407 .lpddr3_ctrl_phy_reset = 0x1,