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Searched refs:lfsr_wr_rd_dm_bank_0_wl_1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_sdram_config.c218 .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h152 u8 lfsr_wr_rd_dm_bank_0_wl_1; member
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c1075 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; in rw_mgr_mem_calibrate_write_test_issue()