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Searched refs:lcdc (Results 1 – 25 of 93) sorted by relevance

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/openbmc/linux/drivers/video/fbdev/omap/
H A Dlcdc.c69 } lcdc; variable
73 lcdc.irq_mask |= mask; in enable_irqs()
78 lcdc.irq_mask &= ~mask; in disable_irqs()
109 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */ in enable_controller()
131 init_completion(&lcdc.last_frame_complete); in disable_controller()
133 if (!wait_for_completion_timeout(&lcdc.last_frame_complete, in disable_controller()
135 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n"); in disable_controller()
146 dev_err(lcdc.fbdev->dev, in reset_controller()
155 dev_err(lcdc.fbdev->dev, in reset_controller()
173 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par; in setup_lcd_dma()
[all …]
H A DMakefile13 objs-yy := omapfb_main.o lcdc.o
/openbmc/u-boot/drivers/video/sunxi/
H A Dlcdc.c30 void lcdc_init(struct sunxi_lcdc_reg * const lcdc) in lcdc_init() argument
33 writel(0, &lcdc->ctrl); /* Disable tcon */ in lcdc_init()
34 writel(0, &lcdc->int0); /* Disable all interrupts */ in lcdc_init()
37 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); in lcdc_init()
40 writel(0xffffffff, &lcdc->tcon0_io_tristate); in lcdc_init()
41 writel(0xffffffff, &lcdc->tcon1_io_tristate); in lcdc_init()
44 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth) in lcdc_enable() argument
46 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); in lcdc_enable()
48 setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); in lcdc_enable()
49 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); in lcdc_enable()
[all …]
H A Dsunxi_lcd.c42 struct sunxi_lcdc_reg * const lcdc = in sunxi_lcd_enable() local
53 lcdc_init(lcdc); in sunxi_lcd_enable()
57 lcdc_tcon0_mode_set(lcdc, edid, clk_div, false, in sunxi_lcd_enable()
59 lcdc_enable(lcdc, priv->panel_bpp); in sunxi_lcd_enable()
H A DMakefile6 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o simplefb_common.o lcdc.o tve_common.o ../videomodes.o
7 obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o sunxi_…
H A Dsunxi_dw_hdmi.c258 struct sunxi_lcdc_reg *lcdc; in sunxi_dw_hdmi_lcdc_init() local
261 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; in sunxi_dw_hdmi_lcdc_init()
271 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE; in sunxi_dw_hdmi_lcdc_init()
282 lcdc_init(lcdc); in sunxi_dw_hdmi_lcdc_init()
283 lcdc_tcon1_mode_set(lcdc, edid, false, false); in sunxi_dw_hdmi_lcdc_init()
284 lcdc_enable(lcdc, bpp); in sunxi_dw_hdmi_lcdc_init()
H A Dsunxi_display.c525 struct sunxi_lcdc_reg * const lcdc = in sunxi_lcdc_init() local
545 lcdc_init(lcdc); in sunxi_lcdc_init()
647 struct sunxi_lcdc_reg * const lcdc = local
674 lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
683 struct sunxi_lcdc_reg * const lcdc = local
690 lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
928 struct sunxi_lcdc_reg * const lcdc = local
943 lcdc_enable(lcdc, sunxi_display.depth);
973 lcdc_enable(lcdc, sunxi_display.depth);
985 lcdc_enable(lcdc, sunxi_display.depth);
[all …]
/openbmc/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c143 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev); in imx_lcdc_update_hw_registers() local
150 writel(addr, lcdc->base + IMX21LCDC_LSSAR); in imx_lcdc_update_hw_registers()
157 clk_disable_unprepare(lcdc->clk_per); in imx_lcdc_update_hw_registers()
162 writel(framesize, lcdc->base + IMX21LCDC_LSR); in imx_lcdc_update_hw_registers()
168 writel(lhcr, lcdc->base + IMX21LCDC_LHCR); in imx_lcdc_update_hw_registers()
174 writel(lvcr, lcdc->base + IMX21LCDC_LVCR); in imx_lcdc_update_hw_registers()
176 lpcr = readl(lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
179 writel(lpcr, lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
182 writel(new_state->fb->pitches[0] / 4, lcdc->base + IMX21LCDC_LVPWR); in imx_lcdc_update_hw_registers()
186 clk_prepare_enable(lcdc->clk_per); in imx_lcdc_update_hw_registers()
[all …]
H A DMakefile1 obj-$(CONFIG_DRM_IMX_LCDC) += imx-lcdc.o
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Datmel,lcdc.txt6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
30 compatible = "atmel,at91sam9g45-lcdc";
44 compatible = "atmel,at91sam9263-lcdc";
H A Dmarvell,pxa2xx-lcdc.txt6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
25 compatible = "marvell,pxa2xx-lcdc";
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-msm8660.c752 MSM_PIN_FUNCTION(lcdc),
773 PINGROUP(0, lcdc, dsub, _, _, _, _, _),
774 PINGROUP(1, lcdc, dsub, _, _, _, _, _),
775 PINGROUP(2, lcdc, dsub, _, _, _, _, _),
776 PINGROUP(3, lcdc, dsub, _, _, _, _, _),
777 PINGROUP(4, lcdc, dsub, _, _, _, _, _),
778 PINGROUP(5, lcdc, dsub, _, _, _, _, _),
779 PINGROUP(6, lcdc, dsub, _, _, _, _, _),
780 PINGROUP(7, lcdc, dsub, _, _, _, _, _),
781 PINGROUP(8, lcdc, dsub, _, _, _, _, _),
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/openbmc/linux/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.c290 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); in lcdc_write_chan()
292 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + in lcdc_write_chan()
299 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + in lcdc_write_chan_mirror()
306 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); in lcdc_read_chan()
312 iowrite32(data, ovl->channel->lcdc->base + reg); in lcdc_write_overlay()
313 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET); in lcdc_write_overlay()
400 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); in lcdc_sys_write_index()
401 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_index()
402 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | in lcdc_sys_write_index()
404 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_index()
[all …]
H A Dsh_mobile_lcdcfb.h44 struct sh_mobile_lcdc_chan *lcdc; member
57 struct sh_mobile_lcdc_priv *lcdc; member
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dlcdc.h117 void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
118 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
119 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
123 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
/openbmc/linux/drivers/gpu/drm/imx/
H A DMakefile5 obj-$(CONFIG_DRM_IMX_LCDC) += lcdc/
H A DKconfig5 source "drivers/gpu/drm/imx/lcdc/Kconfig"
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi154 lcdc: lcd-controller@40500000 { label
155 compatible = "marvell,pxa2xx-lcdc";
H A Dpxa300-raumfeld-controller.dts149 &lcdc {
258 lcdc_pins: lcdc-pins {
/openbmc/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dtilcdc.txt41 tfp410 DVI encoder or lcd panel to lcdc
58 ti,hwmods = "lcdc";
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts34 &lcdc {
H A Dimx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts34 &lcdc {
H A Dimx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts53 &lcdc {
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3128.dtsi663 lcdc {
664 lcdc_dclk: lcdc-dclk {
668 lcdc_den: lcdc-den {
672 lcdc_hsync: lcdc-hsync {
676 lcdc_vsync: lcdc-vsync {
680 lcdc_rgb24: lcdc-rgb24 {
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt124 lcdc: lcdc@40008000 {

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