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Searched refs:ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7516 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_0_1_offset.h12359 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_2_1_0_offset.h12963 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_1_0_offset.h13203 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_2_offset.h14173 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_2_1_offset.h13649 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_5_offset.h14279 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_4_offset.h274 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_2_0_offset.h13670 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_1_6_offset.h14770 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_0_2_offset.h15252 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_2_0_0_offset.h16627 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
H A Ddcn_3_0_0_offset.h16975 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h17016 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … macro