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Searched refs:ixAZALIA_INPUT_CRC1_CHANNEL5 (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_d.h6713 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 macro
H A Ddce_11_0_d.h6875 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 macro
H A Ddce_11_2_d.h8220 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 macro
H A Ddce_12_0_offset.h18101 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7384 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_0_1_offset.h12227 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_2_1_0_offset.h12831 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_1_0_offset.h13071 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_2_offset.h14041 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_2_1_offset.h13517 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_5_offset.h14147 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_4_offset.h197 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_2_0_offset.h13538 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_1_6_offset.h14638 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_0_2_offset.h15120 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_2_0_0_offset.h16495 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro
H A Ddcn_3_0_0_offset.h16844 #define ixAZALIA_INPUT_CRC1_CHANNEL5 … macro