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Searched refs:ixAZALIA_INPUT_CRC1_CHANNEL0 (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_d.h6708 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 macro
H A Ddce_11_0_d.h6870 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 macro
H A Ddce_11_2_d.h8215 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 macro
H A Ddce_12_0_offset.h18096 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7379 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_0_1_offset.h12222 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_2_1_0_offset.h12826 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_1_0_offset.h13066 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_2_offset.h14036 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_2_1_offset.h13512 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_5_offset.h14142 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_4_offset.h192 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_2_0_offset.h13533 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_6_offset.h14633 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_0_2_offset.h15115 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_2_0_0_offset.h16490 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro
H A Ddcn_3_0_0_offset.h16839 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … macro