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Searched refs:ixAZALIA_CRC1_CHANNEL0 (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h5463 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
H A Ddce_10_0_d.h6734 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
H A Ddce_11_0_d.h6896 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
H A Ddce_11_2_d.h8241 #define ixAZALIA_CRC1_CHANNEL0 0x0 macro
H A Ddce_12_0_offset.h18120 #define ixAZALIA_CRC1_CHANNEL0 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7403 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_0_1_offset.h12246 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_2_1_0_offset.h12850 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_1_0_offset.h13090 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_2_offset.h14060 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_2_1_offset.h13536 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_5_offset.h14166 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_4_offset.h216 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_2_0_offset.h13557 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_1_6_offset.h14657 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_0_2_offset.h15139 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_2_0_0_offset.h16514 #define ixAZALIA_CRC1_CHANNEL0 … macro
H A Ddcn_3_0_0_offset.h16863 #define ixAZALIA_CRC1_CHANNEL0 … macro