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Searched refs:ixAZALIA_CRC0_CHANNEL1 (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h5451 #define ixAZALIA_CRC0_CHANNEL1 0x1 macro
H A Ddce_10_0_d.h6722 #define ixAZALIA_CRC0_CHANNEL1 0x1 macro
H A Ddce_11_0_d.h6884 #define ixAZALIA_CRC0_CHANNEL1 0x1 macro
H A Ddce_11_2_d.h8229 #define ixAZALIA_CRC0_CHANNEL1 0x1 macro
H A Ddce_12_0_offset.h18109 #define ixAZALIA_CRC0_CHANNEL1 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h7392 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_0_1_offset.h12235 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_2_1_0_offset.h12839 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_1_0_offset.h13079 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_1_2_offset.h14049 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_2_1_offset.h13525 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_1_5_offset.h14155 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_1_4_offset.h205 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_2_0_offset.h13546 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_1_6_offset.h14646 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_0_2_offset.h15128 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_2_0_0_offset.h16503 #define ixAZALIA_CRC0_CHANNEL1 … macro
H A Ddcn_3_0_0_offset.h16852 #define ixAZALIA_CRC0_CHANNEL1 … macro