Searched refs:is_fiq (Results 1 – 4 of 4) sorted by relevance
/openbmc/qemu/hw/intc/ |
H A D | imx_avic.c | 44 VMSTATE_UINT64(is_fiq, IMXAVICState), 66 flags = new & s->is_fiq; in imx_avic_update() 69 flags = new & ~s->is_fiq; in imx_avic_update() 133 return s->is_fiq >> 32; in imx_avic_read() 136 return s->is_fiq & 0xffffffffULL; in imx_avic_read() 156 uint64_t flags = s->pending & s->enabled & ~s->is_fiq; in imx_avic_read() 177 uint64_t flags = s->pending & s->enabled & s->is_fiq; in imx_avic_read() 196 return (s->pending & s->enabled & ~s->is_fiq) >> 32; in imx_avic_read() 199 return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL; in imx_avic_read() 202 return (s->pending & s->enabled & s->is_fiq) >> 32; in imx_avic_read() [all …]
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H A D | omap_intc.c | 61 static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq) in omap_inth_sir_update() argument 74 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); in omap_inth_sir_update() 86 s->sir_intr[is_fiq] = sir_intr; in omap_inth_sir_update() 89 static inline void omap_inth_update(OMAPIntcState *s, int is_fiq) in omap_inth_update() argument 96 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); in omap_inth_update() 98 if (s->new_agr[is_fiq] & has_intr & s->mask) { in omap_inth_update() 99 s->new_agr[is_fiq] = 0; in omap_inth_update() 100 omap_inth_sir_update(s, is_fiq); in omap_inth_update() 101 qemu_set_irq(s->parent_intr[is_fiq], 1); in omap_inth_update()
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/openbmc/qemu/include/hw/intc/ |
H A D | imx_avic.h | 48 uint64_t is_fiq; member
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/openbmc/qemu/hw/arm/ |
H A D | strongarm.c | 92 uint32_t is_fiq; member 111 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); in strongarm_pic_update() 112 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); in strongarm_pic_update() 135 return s->pending & ~s->is_fiq & s->enabled; in strongarm_pic_mem_read() 139 return s->is_fiq; in strongarm_pic_mem_read() 143 return s->pending & s->is_fiq & s->enabled; in strongarm_pic_mem_read() 164 s->is_fiq = value; in strongarm_pic_mem_write() 212 VMSTATE_UINT32(is_fiq, StrongARMPICState),
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