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Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c95 } interrupt_status_offsets[6] = { { variable
2979 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()
2985 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()
2996 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
3100 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3101 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
H A Ddce_v8_0.c90 } interrupt_status_offsets[6] = { { variable
3067 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()
3073 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()
3084 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
3188 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3189 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
H A Ddce_v10_0.c90 } interrupt_status_offsets[] = { { variable
3247 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()
3252 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3264 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3293 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3294 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
H A Ddce_v11_0.c94 } interrupt_status_offsets[] = { { variable
3378 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()
3384 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()
3396 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()
3425 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3426 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()