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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dintel-gma.txt9 - compatible : "intel,gma";
12 - intel,dp-hotplug : values for digital port hotplug, one cell per value for
14 - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D
15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
18 - intel,panel-power-up-delay : T1+T2 time sequence
19 - intel,panel-power-down-delay : T3 time sequence
20 - intel,panel-power-backlight-on-delay : T5 time sequence
21 - intel,panel-power-backlight-off-delay : Tx time sequence
23 - intel,cpu-backlight : Value for CPU Backlight PWM
24 - intel,pch-backlight : Value for PCH Backlight PWM
[all …]
/openbmc/u-boot/arch/x86/dts/
H A Dcougarcanyon2.dts8 #include <dt-bindings/interrupt-router/intel-irq.h>
19 compatible = "intel,cougarcanyon2", "intel,chiefriver";
39 compatible = "intel,core-gen3";
41 intel,apic-id = <0>;
46 compatible = "intel,core-gen3";
48 intel,apic-id = <1>;
53 compatible = "intel,core-gen3";
55 intel,apic-id = <2>;
60 compatible = "intel,core-gen3";
62 intel,apic-id = <3>;
[all …]
H A Dchromebook_samus.dts14 compatible = "google,samus", "intel,broadwell";
32 compatible = "intel,core-i3-gen5";
34 intel,apic-id = <0>;
35 intel,slow-ramp = <3>;
40 compatible = "intel,core-i3-gen5";
42 intel,apic-id = <1>;
47 compatible = "intel,core-i3-gen5";
49 intel,apic-id = <2>;
54 compatible = "intel,core-i3-gen5";
56 intel,apic-id = <3>;
[all …]
H A Dbaytrail_som-db5800-som-6867.dts11 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
85 compatible = "intel,baytrail-cpu";
87 intel,apic-id = <0>;
92 compatible = "intel,baytrail-cpu";
94 intel,apic-id = <2>;
99 compatible = "intel,baytrail-cpu";
101 intel,apic-id = <4>;
106 compatible = "intel,baytrail-cpu";
[all …]
H A Dbayleybay.dts10 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "intel,bayleybay", "intel,baytrail";
42 compatible = "intel,baytrail-cpu";
44 intel,apic-id = <0>;
49 compatible = "intel,baytrail-cpu";
51 intel,apic-id = <2>;
56 compatible = "intel,baytrail-cpu";
58 intel,apic-id = <4>;
63 compatible = "intel,baytrail-cpu";
65 intel,apic-id = <6>;
[all …]
H A Dchromebook_link.dts16 compatible = "google,link", "intel,celeron-ivybridge";
34 compatible = "intel,core-gen3";
36 intel,apic-id = <0>;
41 compatible = "intel,core-gen3";
43 intel,apic-id = <1>;
48 compatible = "intel,core-gen3";
50 intel,apic-id = <2>;
55 compatible = "intel,core-gen3";
57 intel,apic-id = <3>;
67 intel,duplicate-por;
[all …]
H A Dedison.dts9 #include <dt-bindings/interrupt-router/intel-irq.h>
17 compatible = "intel,edison";
37 intel,apic-id = <0>;
44 intel,apic-id = <2>;
59 compatible = "intel,mid-uart";
67 compatible = "intel,mid-uart";
75 compatible = "intel,mid-uart";
83 compatible = "intel,sdhci-tangier";
92 compatible = "intel,sdhci-tangier";
98 compatible = "intel,pmu-mid";
[all …]
H A Dconga-qeval20-qa3-e3845.dts11 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
73 compatible = "intel,baytrail-cpu";
75 intel,apic-id = <0>;
80 compatible = "intel,baytrail-cpu";
82 intel,apic-id = <2>;
87 compatible = "intel,baytrail-cpu";
89 intel,apic-id = <4>;
94 compatible = "intel,baytrail-cpu";
[all …]
H A Dgalileo.dts9 #include <dt-bindings/interrupt-router/intel-irq.h>
18 compatible = "intel,galileo", "intel,quark";
40 intel,apic-id = <0>;
49 compatible = "intel,quark-mrc";
96 compatible = "intel,pch7";
101 compatible = "intel,irq-router";
102 intel,pirq-config = "pci";
103 intel,actl-addr = <0x58>;
104 intel,pirq-link = <0x60 8>;
105 intel,pirq-mask = <0xdef8>;
[all …]
H A Ddfi-bt700.dtsi9 #include <dt-bindings/interrupt-router/intel-irq.h>
22 compatible = "intel,x86-pinctrl";
71 compatible = "intel,baytrail-cpu";
73 intel,apic-id = <0>;
78 compatible = "intel,baytrail-cpu";
80 intel,apic-id = <2>;
85 compatible = "intel,baytrail-cpu";
87 intel,apic-id = <4>;
92 compatible = "intel,baytrail-cpu";
94 intel,apic-id = <6>;
[all …]
H A Dcherryhill.dts9 #include <dt-bindings/interrupt-router/intel-irq.h>
19 compatible = "intel,cherryhill", "intel,braswell";
42 intel,apic-id = <0>;
49 intel,apic-id = <2>;
56 intel,apic-id = <4>;
63 intel,apic-id = <6>;
78 compatible = "intel,pch9";
81 compatible = "intel,irq-router";
82 intel,pirq-config = "ibase";
83 intel,ibase-offset = <0x50>;
[all …]
H A Dqemu-x86_q35.dts8 #include <dt-bindings/interrupt-router/intel-irq.h>
50 intel,apic-id = <0>;
69 compatible = "intel,pch9";
73 compatible = "intel,irq-router";
75 intel,pirq-config = "pci";
76 intel,actl-8bit;
77 intel,actl-addr = <0x44>;
78 intel,pirq-link = <0x60 8>;
79 intel,pirq-mask = <0x0e40>;
80 intel,pirq-routing = <
H A Dminnowmax.dts10 #include <dt-bindings/interrupt-router/intel-irq.h>
20 compatible = "intel,minnowmax", "intel,baytrail";
32 compatible = "intel,x86-pinctrl";
99 compatible = "intel,baytrail-cpu";
101 intel,apic-id = <0>;
106 compatible = "intel,baytrail-cpu";
108 intel,apic-id = <4>;
114 compatible = "intel,pci-baytrail", "pci-x86";
124 compatible = "pci8086,0f1c", "intel,pch9";
129 compatible = "intel,irq-router";
[all …]
H A Du-boot.dtsi18 intel-descriptor {
21 intel-me {
47 intel-mrc {
52 intel-fsp {
58 intel-cmc {
64 intel-vga {
70 intel-vbt {
76 intel-refcode {
H A Dqemu-x86_i440fx.dts8 #include <dt-bindings/interrupt-router/intel-irq.h>
39 intel,apic-id = <0>;
58 compatible = "intel,pch7";
62 compatible = "intel,irq-router";
64 intel,pirq-config = "pci";
65 intel,pirq-link = <0x60 4>;
66 intel,pirq-mask = <0x0e40>;
67 intel,pirq-routing = <
H A Dcrownbay.dts8 #include <dt-bindings/interrupt-router/intel-irq.h>
20 compatible = "intel,crownbay", "intel,queensbay";
38 intel,apic-id = <0>;
45 intel,apic-id = <1>;
151 compatible = "intel,pch7";
156 compatible = "intel,irq-router";
157 intel,pirq-config = "pci";
158 intel,actl-addr = <0x58>;
159 intel,pirq-link = <0x60 8>;
160 intel,pirq-mask = <0xcee0>;
[all …]
H A Dchromebox_panther.dts11 compatible = "google,panther", "intel,haswell";
37 compatible = "intel,pch9";
44 compatible = "intel,ich9-spi";
60 compatible = "intel,ich6-gpio";
67 compatible = "intel,ich6-gpio";
74 compatible = "intel,ich6-gpio";
/openbmc/u-boot/doc/device-tree-bindings/ata/
H A Dintel-sata.txt8 - compatible = "intel,pantherpoint-ahci"
9 - intel,sata-mode : string, one of:
13 - intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
15 - intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
16 - intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
22 compatible = "intel,pantherpoint-ahci";
23 intel,sata-mode = "ahci";
24 intel,sata-port-map = <1>;
25 intel,sata-port0-gen3-tx = <0x00880a7f>;
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dintel,irq-router.txt10 - compatible = "intel,irq-router"
11 - intel,pirq-config : Specifies the IRQ routing register programming mechanism.
15 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
16 configuration space, required only if intel,pirq-config = "ibase".
17 - intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
20 - intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
22 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
25 - intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
30 link, as specified by the first cell of intel,pirq-link.
31 - intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
[all …]
H A Dintel-lpc.txt8 - compatible = "intel,lpc"
9 - intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
11 - intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
15 - intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
20 - intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
46 compatible = "intel,lpc";
49 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
51 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
60 intel,gpi-routing = <0 0 0 0 0 0 0 2
63 intel,alt-gp-smi-enable = <0x0100>;
/openbmc/phosphor-dbus-interfaces/gen/com/intel/Control/
H A Dmeson.build5 sdbusplus_current_path = 'com/intel/Control'
8 'com/intel/Control/NMISource__markdown'.underscorify(),
9 input: ['../../../../yaml/com/intel/Control/NMISource.interface.yaml'],
22 'com/intel/Control/NMISource',
30 'com/intel/Control/OCOTShutdownPolicy__markdown'.underscorify(),
32 '../../../../yaml/com/intel/Control/OCOTShutdownPolicy.interface.yaml',
46 'com/intel/Control/OCOTShutdownPolicy',
/openbmc/openbmc/meta-intel-openbmc/conf/machine/include/
H A Dintel.inc13 PREFERRED_PROVIDER_virtual/obmc-chassis-mgmt = "packagegroup-intel-apps"
14 PREFERRED_PROVIDER_virtual/obmc-fan-mgmt = "packagegroup-intel-apps"
15 PREFERRED_PROVIDER_virtual/obmc-flash-mgmt = "packagegroup-intel-apps"
16 PREFERRED_PROVIDER_virtual/obmc-system-mgmt = "packagegroup-intel-apps"
20 OVERRIDES .= ":intel"
22 OBMC_ORG_YAML_SUBDIRS += "com/intel"
/openbmc/entity-manager/configurations/
H A Dmeson.build84 'intel/1ux16_riser.json',
85 'intel/2ux8_riser.json',
86 'intel/8x25_hsbp.json',
87 'intel/a2ul16riser.json',
88 'intel/a2ux8x4riser.json',
89 'intel/ahw1um2riser.json',
90 'intel/axx1p100hssi_aic.json',
91 'intel/axx2prthdhd.json',
92 'intel/bnp_baseboard.json',
93 'intel/f1u12x25_hsb
[all...]
/openbmc/phosphor-dbus-interfaces/gen/com/intel/Protocol/PECI/
H A Dmeson.build4 sdbusplus_current_path = 'com/intel/Protocol/PECI'
7 'com/intel/Protocol/PECI/Raw__markdown'.underscorify(),
8 input: ['../../../../../yaml/com/intel/Protocol/PECI/Raw.interface.yaml'],
21 'com/intel/Protocol/PECI/Raw',
/openbmc/phosphor-dbus-interfaces/gen/com/intel/Control/NMISource/
H A Dmeson.build3 sdbusplus_current_path = 'com/intel/Control/NMISource'
6 'com/intel/Control/NMISource__cpp'.underscorify(),
7 input: ['../../../../../yaml/com/intel/Control/NMISource.interface.yaml'],
26 'com/intel/Control/NMISource',

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