| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
13 - FEAT_AES (AESD and AESE instructions)
15 - FEAT_BF16 (AArch64 BFloat16 instructions)
17 - FEAT_CRC32 (CRC32 instructions)
38 - FEAT_FPAC (Faulting on AUT* instructions)
74 - FEAT_PMULL (PMULL, PMULL2 instructions)
86 - FEAT_SHA1 (SHA1 instructions)
87 - FEAT_SHA256 (SHA256 instructions)
90 - FEAT_SM3 (Advanced SIMD SM3 instructions)
91 - FEAT_SM4 (Advanced SIMD SM4 instructions)
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | legacy_instructions.rst | 2 Legacy instructions
6 emulation of instructions which have been deprecated, or obsoleted in
18 Generates undefined instruction abort. Default for instructions that
27 instructions, .e.g., CP15 barriers
34 instructions. Using hardware execution generally provides better
36 about the use of the deprecated instructions.
39 architecture. Deprecated instructions should default to emulation
40 while obsolete instructions must be undefined by default.
45 Supported legacy instructions
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| /openbmc/linux/drivers/watchdog/ |
| H A D | wdat_wdt.c | 119 if (action >= ARRAY_SIZE(wdat->instructions)) in wdat_wdt_run_action()
122 if (!wdat->instructions[action]) in wdat_wdt_run_action()
376 struct list_head *instructions; in wdat_wdt_probe() local
423 instructions = wdat->instructions[action]; in wdat_wdt_probe()
424 if (!instructions) { in wdat_wdt_probe()
425 instructions = devm_kzalloc(dev, in wdat_wdt_probe()
426 sizeof(*instructions), in wdat_wdt_probe()
428 if (!instructions) in wdat_wdt_probe()
431 INIT_LIST_HEAD(instructions); in wdat_wdt_probe()
432 wdat->instructions[action] = instructions; in wdat_wdt_probe()
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| /openbmc/linux/Documentation/bpf/ |
| H A D | linux-notes.rst | 10 Byte swap instructions
15 Jump instructions
45 Legacy BPF Packet access instructions
49 <instruction-set.html#legacy-bpf-packet-access-instructions>`_,
50 Linux has special eBPF instructions for access to packet data that have been
54 The instructions come in two forms: ``BPF_ABS | <size> | BPF_LD`` and
57 These instructions are used to access packet data and can only be used when
63 These instructions have seven implicit operands:
72 These instructions have an implicit program exit condition as well. If an
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| H A D | clang-notes.rst | 17 Arithmetic instructions
23 Jump instructions
32 Clang can generate atomic instructions by default when ``-mcpu=v3`` is
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| H A D | bpf_design_QA.rst | 93 It's the maximum number of instructions that the unprivileged bpf
95 Like the maximum number of instructions that can be explored during
119 Q: LD_ABS and LD_IND instructions vs C code
129 Q: BPF instructions mapping not one-to-one to native CPU
131 Q: It seems not all BPF instructions are one-to-one to native CPU.
149 of LD_ABS insn). Those instructions need to invoke epilogue and
156 due to lack of these compare instructions and they were added.
157 These two instructions is a perfect example what kind of new BPF
158 instructions are acceptable and can be added in the future.
159 These two already had equivalent instructions in native CPUs.
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| /openbmc/u-boot/doc/ |
| H A D | README.NDS32 | 13 - 16-bit instructions as a frequently used subset of 32-bit instructions.
17 instructions.
18 - Rich load/store instructions for...
23 - Non-bus locking synchronization instructions.
24 - PC relative jump and PC read instructions for efficient position independent
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| H A D | README.AX25 | 16 - RV64I base integer instructions
17 - RVC for 16-bit compressed instructions
18 - RVM for multiplication and division instructions
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| /openbmc/qemu/docs/devel/ |
| H A D | tcg-icount.rst | 27 At its heart icount is simply a count of executed instructions which
29 executed instructions can then be used to calculate QEMU_CLOCK_VIRTUAL
35 To be able to calculate the number of executed instructions the
36 translator starts by allocating a budget of instructions to be
37 executed. The budget of instructions is limited by how long it will be
45 number of instructions the translation block would execute. If this
48 number of instructions to take the budget to 0 meaning whatever timer
61 - restore un-executed instructions to the icount budget
65 .. [1] sometimes two instructions if dealing with delay slots
71 correct and accurate clock. IO port instructions and accesses to
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| /openbmc/linux/Documentation/bpf/standardization/ |
| H A D | instruction-set.rst | 15 mnemonic functions when describing the semantics of instructions.
143 Note that most instructions do not use all of the fields.
188 Arithmetic and jump instructions
216 Arithmetic instructions
271 Note that most instructions have instruction offset of 0. Only three instructions
295 Byte swap instructions
340 Jump instructions
414 Load and store instructions
431 BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
545 64-bit immediate instructions
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| /openbmc/linux/tools/perf/Documentation/ |
| H A D | itrace.txt | 1 i synthesize instructions events
33 for instructions events can be specified in units of:
35 i instructions
41 Also the call chain size (default 16, max. 1024) for instructions or
45 instructions or transactions events can be specified.
51 It is also possible to skip events generated (instructions, branches, transactions,
56 skips the first million instructions.
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | swp_emulation.rst | 4 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommends
5 moving to the load-locked/store-conditional instructions LDREX and STREX.
8 instructions, triggering an undefined instruction exception when executed.
9 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
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| H A D | kernel_mode_neon.rst | 7 * Use only NEON instructions, or VFP instructions that don't rely on support
19 It is possible to use NEON instructions (and in some cases, VFP instructions) in
24 may call schedule()], as NEON or VFP instructions will be executed in a
43 should be called before any kernel mode NEON or VFP instructions are issued.
74 Such software assistance is currently not implemented for VFP instructions
82 kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
86 instructions appearing in unexpected places if no special care is taken.
98 both NEON and VFP instructions will only ever appear in designated compilation
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| /openbmc/linux/tools/testing/selftests/powerpc/pmu/ |
| H A D | count_instructions.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument
38 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
45 expected = instructions + overhead; in do_count_loop()
53 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
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| H A D | count_stcx_fail.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument
39 thirty_two_instruction_loop_with_ll_sc(instructions >> 5, &dummy); in do_count_loop()
47 expected = instructions + overhead + (events[2].result.value * 10); in do_count_loop()
57 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
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| /openbmc/linux/Documentation/arch/x86/x86_64/ |
| H A D | fsgs.rst | 69 Accessing FS/GS base with the FSGSBASE instructions
73 instructions to access the FS and GS base registers directly from user
74 space. These instructions are also supported on AMD Family 17H CPUs. The
75 following instructions are available:
90 FSGSBASE instructions enablement
92 The instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If
95 The availability of the instructions does not enable them
103 instructions will fault with a #UD exception.
107 kernel has FSGSBASE instructions enabled and applications can use them.
125 FSGSBASE instructions compiler support
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| /openbmc/linux/tools/perf/tests/shell/ |
| H A D | stat+shadow_stat.sh | 15 perf stat -a --no-big-num -e cycles,instructions sleep 1 2>&1 | \
16 grep -e cycles -e instructions | \
46 perf stat -a -A --no-big-num -e cycles,instructions sleep 1 2>&1 | \
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| /openbmc/linux/tools/testing/selftests/powerpc/pmu/ebb/ |
| H A D | instruction_count_test.c | 25 static int do_count_loop(struct event *event, uint64_t instructions, in do_count_loop() argument
37 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
46 expected = instructions + overhead; in do_count_loop()
51 printf("Looped for %lu instructions, overhead %lu\n", instructions, overhead); in do_count_loop()
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| /openbmc/openbmc/poky/meta/conf/machine/include/arm/ |
| H A D | feature-arm-crc.inc | 1 # Cyclic Redundancy Check (CRC) instructions for armv8-a and armv8-r
3 TUNEVALID[crc] = "Enable instructions for ARMv8 Cyclic Redundancy Check (CRC)"
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| H A D | feature-arm-crypto.inc | 1 # Cryptographic instructions for:
4 TUNEVALID[crypto] = "Enable cryptographic instructions for ARMv8"
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| H A D | feature-arm-simd.inc | 1 # Advanced SIMD and floating-point instructions for armv7-a, armv7ve,
4 TUNEVALID[simd] = "Enable instructions for Advanced SIMD and floating-point units"
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| H A D | feature-arm-sve.inc | 4 TUNEVALID[sve] = "Enable SVE instructions for ARMv8"
7 TUNEVALID[sve2] = "Enable SVE2 instructions for ARMv8"
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| /openbmc/linux/arch/sparc/crypto/ |
| H A D | Kconfig | 37 Architecture: sparc64 using crypto instructions, when available
57 Architecture: sparc64 using crypto instructions, when available
67 Architecture: sparc64 using crypto instructions, when available
77 Architecture: sparc64 using crypto instructions
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| /openbmc/linux/tools/memory-model/ |
| H A D | linux-kernel.bell | 20 instructions R[{'once,'acquire,'noreturn}]
21 instructions W[{'once,'release}]
22 instructions RMW[{'once,'acquire,'release}]
36 instructions F[Barriers]
40 instructions SRCU[SRCU]
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| /openbmc/linux/Documentation/virt/kvm/ |
| H A D | ppc-pv.rst | 9 instructions and can emulate them accordingly.
12 instructions that needlessly return us to the hypervisor even though they
15 This is what the PPC PV interface helps with. It takes privileged instructions
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
36 up the hypercall. To call a hypercall, just call these instructions.
138 Patched instructions
141 The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions
147 also act on the shared page. So calling privileged instructions still works as
187 Some instructions require more logic to determine what's going on than a load
189 RAM around where we can live translate instructions to. What happens is the
|