| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
22 - FEAT_AES (AESD and AESE instructions)
29 - FEAT_BF16 (AArch64 BFloat16 instructions)
34 - FEAT_CRC32 (CRC32 instructions)
36 - FEAT_CSSC (Common Short Sequence Compression instructions)
44 - FEAT_DIT (Data Independent Timing instructions)
52 - FEAT_DotProd (Advanced SIMD dot product instructions)
55 - FEAT_EBF16 (AArch64 Extended BFloat16 instructions)
66 - FEAT_FCMA (Floating-point complex number instructions)
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| /openbmc/u-boot/doc/ |
| H A D | README.NDS32 | 13 - 16-bit instructions as a frequently used subset of 32-bit instructions.
17 instructions.
18 - Rich load/store instructions for...
23 - Non-bus locking synchronization instructions.
24 - PC relative jump and PC read instructions for efficient position independent
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| H A D | README.AX25 | 16 - RV64I base integer instructions
17 - RVC for 16-bit compressed instructions
18 - RVM for multiplication and division instructions
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| /openbmc/qemu/docs/devel/ |
| H A D | tcg-icount.rst | 27 At its heart icount is simply a count of executed instructions which
29 executed instructions can then be used to calculate QEMU_CLOCK_VIRTUAL
35 To be able to calculate the number of executed instructions the
36 translator starts by allocating a budget of instructions to be
37 executed. The budget of instructions is limited by how long it will be
45 number of instructions the translation block would execute. If this
48 number of instructions to take the budget to 0 meaning whatever timer
61 - restore un-executed instructions to the icount budget
65 .. [1] sometimes two instructions if dealing with delay slots
71 correct and accurate clock. IO port instructions an
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| /openbmc/openbmc/poky/meta/conf/machine/include/arm/ |
| H A D | feature-arm-crc.inc | 1 # Cyclic Redundancy Check (CRC) instructions for armv8-a and armv8-r
3 TUNEVALID[crc] = "Enable instructions for ARMv8 Cyclic Redundancy Check (CRC)"
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| H A D | feature-arm-crypto.inc | 1 # Cryptographic instructions for:
4 TUNEVALID[crypto] = "Enable cryptographic instructions for ARMv8"
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| H A D | feature-arm-sve.inc | 4 TUNEVALID[sve] = "Enable SVE instructions for ARMv8"
7 TUNEVALID[sve2] = "Enable SVE2 instructions for ARMv8"
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| H A D | feature-arm-simd.inc | 1 # Advanced SIMD and floating-point instructions for armv7-a, armv7ve,
4 TUNEVALID[simd] = "Enable instructions for Advanced SIMD and floating-point units"
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| H A D | arch-arm64.inc | 5 TUNEVALID[aarch64] = "Enable instructions for aarch64"
41 # Emit branch protection (PAC/BTI) instructions. On hardware that doesn't
42 # support these they're meaningless NOP instructions, so there's very little
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| H A D | feature-arm-idiv.inc | 1 TUNEVALID[idiv] = "ARM-state integer division instructions"
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | loong-ext.decode | 1 # Loongson 64-bit Extension instructions
9 # Appendix A: new integer instructions
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| H A D | lcsr.decode | 1 # Loongson CSR instructions
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| /openbmc/qemu/docs/system/openrisc/ |
| H A D | emulation.rst | 13 for most Class II (optional) instructions.
15 For information on all OpenRISC instructions please refer to the latest
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| /openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/tremor/tremor/ |
| H A D | tremor-arm-thumb2.patch | 3 Subject: [PATCH] tremor: add IT instructions for arm thumb2 tune flags.
7 In Thumb-2, most instructions do not have a built in condition code (except for
8 conditional branches). Instead, short sequences of instructions which are to be
10 describes the condition and which of the following instructions should be
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | processor-ctrl-impl.c.inc | 2 * Power ISA decode for Storage Control instructions
28 * Before Power ISA 2.07, processor control instructions were only
52 * Before Power ISA 2.07, processor control instructions were only
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| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | README | 74 Build instructions:
87 on EVM. See instructions at below link for installing CCS on a Windows PC.
91 on EVM. Follow instructions at
98 and Power ON the EVM. Follow instructions to connect serial port of EVM to
104 The instructions provided in the above link uses a script for
132 SPI NOR Flash programming instructions
135 instructions:
153 AEMIF NAND Flash programming instructions
156 instructions:
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | README | 6 This program executes most of the 16 bit and 32 bit x86 instructions and
21 This program executes most SSE/AVX instructions and generates a text output,
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/ |
| H A D | scp-firmware-sgi575.inc | 1 # SGI575 specific SCP configurations and build instructions
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| /openbmc/u-boot/doc/imx/mkimage/ |
| H A D | mxsimage.txt | 39 subsequent instructions or code. Exactly one section must be selected
40 as bootable, usually the one containing the instructions and data to
49 - After a "TAG" instruction, any of the following instructions may follow
106 - The DCD block must be followed by one of the following instructions. All
107 of the instructions operate either on 1, 2 or 4 bytes. This is selected by
149 Here is a mapping between the above instructions and the BootROM output:
169 instructions contained in the SB image. It will also check if the various
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| /openbmc/qemu/docs/about/ |
| H A D | emulation.rst | 115 instructions to trigger a semihosting call are typically reserved
213 ops to count and break down the hint instructions by type.
289 instructions (Default: N = 100000000)
309 number of instructions executed on each core/thread::
338 - Only instrument instructions matching the string prefix
341 instructions have executed since the last execution. For
449 count, number of instructions and execution count. This will work best
507 types of instructions. It has a number of options to refine which get
509 instructions to break it down fully, so for example to see all the system
647 The execlog tool traces executed instructions wit
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| /openbmc/openbmc/meta-openpower/recipes-phosphor/debug/openpower-debug-collector/ |
| H A D | openpower-debug-collector-watchdog@.service | 4 After=op-stop-instructions@%i.service
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| /openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/ |
| H A D | use-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch | 7 -march/-mcpu/-mfpu flags to support the instructions being tested.
11 For tests requiring armv7ve instructions, ensure that we set both
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| /openbmc/openpower-occ-control/service_files/ |
| H A D | op-occ-disable@.service | 5 Before=op-stop-instructions@%i.service
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | neon-ls.decode | 22 # Encodings for Neon load/store instructions where the T32 encoding
24 # More specifically, this file covers instructions where the A32 encoding is
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| /openbmc/qemu/ |
| H A D | .gdbinit | 2 # follow the instructions it prints. They boil down to adding the following to
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