| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 62 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor() argument
66 clk_div = input_rate / output_rate; in clk_get_divisor()
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| /openbmc/u-boot/drivers/clk/aspeed/ |
| H A D | clk_ast2400.c | 269 ulong input_rate; member
278 static bool ast2400_get_clock_config_default(ulong input_rate, in ast2400_get_clock_config_default() argument
287 if (default_cfg->input_rate == input_rate && in ast2400_get_clock_config_default()
307 static ulong ast2400_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2400_calc_clock_config() argument
314 const ulong input_rate_khz = input_rate / 1000; in ast2400_calc_clock_config()
324 if (ast2400_get_clock_config_default(input_rate, requested_rate, cfg)) in ast2400_calc_clock_config()
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| H A D | clk_ast2500.c | 243 ulong input_rate; member
252 static bool ast2500_get_clock_config_default(ulong input_rate, in ast2500_get_clock_config_default() argument
261 if (default_cfg->input_rate == input_rate && in ast2500_get_clock_config_default()
281 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config() argument
288 const ulong input_rate_khz = input_rate / 1000; in ast2500_calc_clock_config()
298 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) in ast2500_calc_clock_config()
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| /openbmc/u-boot/drivers/spi/ |
| H A D | rk_spi.c | 48 uint input_rate; member
83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
95 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
264 priv->input_rate = ret; in rockchip_spi_probe()
265 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 26 #define RATE_TO_DIV(input_rate, output_rate) \ argument
27 ((input_rate) / (output_rate) - 1);
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3328.c | 28 #define RATE_TO_DIV(input_rate, output_rate) \ argument
29 ((input_rate) / (output_rate) - 1);
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk322x.c | 26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3399.c | 40 #define RATE_TO_DIV(input_rate, output_rate) \ argument
41 ((input_rate) / (output_rate) - 1);
42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3188.c | 71 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3128.c | 27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3368.c | 41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rv1108.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3288.c | 131 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 1408 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar() argument
1417 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, in clock_calc_best_scalar()
1425 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1428 if (target_rate >= input_rate) in clock_calc_best_scalar()
1433 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1434 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
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