| /openbmc/qemu/target/arm/tcg/ |
| H A D | cpu32.c | 875 { .name = "arm926", .initfn = arm926_initfn }, in pxa270a0_initfn()
876 { .name = "arm946", .initfn = arm946_initfn }, in pxa270a0_initfn()
877 { .name = "arm1026", .initfn = arm1026_initfn }, in pxa270a0_initfn()
883 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, in pxa270a1_initfn()
884 { .name = "arm1136", .initfn = arm1136_initfn }, in pxa270a1_initfn()
885 { .name = "arm1176", .initfn = arm1176_initfn }, in pxa270a1_initfn()
886 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, in pxa270a1_initfn()
887 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, in pxa270a1_initfn()
888 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, in pxa270a1_initfn()
889 { .name = "cortex-a9", .initfn in pxa270a1_initfn()
[all...] |
| H A D | cpu-v7m.c | 281 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
283 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
285 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
287 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
289 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
291 { .name = "cortex-m55", .initfn = cortex_m55_initfn,
|
| H A D | cpu64.c | 1399 { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
1400 { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
1401 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
1402 { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
1407 { .name = "cortex-a78ae", .initfn = aarch64_a78ae_initfn },
1408 { .name = "cortex-a710", .initfn = aarch64_a710_initfn },
1409 { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
1410 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
1411 { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
1412 { .name = "neoverse-n2", .initfn
[all...] |
| /openbmc/qemu/include/hw/i386/ |
| H A D | pc.h | 304 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
310 mc->init = initfn; \
323 #define DEFINE_PC_VER_MACHINE(namesym, namestr, initfn, isdefault, malias, ...) \
327 initfn(machine); \
301 DEFINE_PC_MACHINE(suffix,namestr,initfn,optsfn) global() argument
320 DEFINE_PC_VER_MACHINE(namesym,namestr,initfn,isdefault,malias,...) global() argument
|
| /openbmc/qemu/target/tricore/ |
| H A D | cpu.c | 225 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ argument
228 .instance_init = initfn, \
|
| /openbmc/qemu/target/avr/ |
| H A D | cpu.c | 395 void (*initfn)(Object *obj); member
399 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ argument
402 .instance_init = initfn, \
|
| /openbmc/qemu/target/alpha/ |
| H A D | cpu.c | 300 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ argument
303 .instance_init = initfn, \
|
| /openbmc/qemu/target/openrisc/ |
| H A D | cpu.c | 302 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
305 .instance_init = initfn, \
303 DEFINE_OPENRISC_CPU_TYPE(cpu_model,initfn) global() argument
|
| /openbmc/qemu/target/sh4/ |
| H A D | cpu.c | 338 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ argument
343 .instance_init = initfn, \
|
| /openbmc/qemu/target/arm/ |
| H A D | cpu64.c | 799 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
800 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
801 { .name = "max", .initfn = aarch64_max_initfn },
803 { .name = "host", .initfn = aarch64_host_initfn },
|
| H A D | cpu.h | 1162 void (*initfn)(Object *obj);
1153 void (*initfn)(Object *obj); global() member
|
| H A D | cpu.c | 1190 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1627 * then it's possible that might have failed in the initfn, but in gt_cntfrq_period_ns()
2410 acc->info->initfn(obj); in arm_cpu_realizefn()
|
| /openbmc/qemu/target/hexagon/ |
| H A D | cpu.c | 379 #define DEFINE_CPU(type_name, initfn) \ argument
383 .instance_init = initfn \
|
| /openbmc/qemu/target/loongarch/ |
| H A D | cpu.c | 735 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ in loongarch_set_lasx()
738 .instance_init = initfn, \ in loongarch_set_lasx()
993 DEFINE_LOONGARCH_CPU_TYPE(size,model,initfn) global() argument
|