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Searched refs:ih_cntl (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts() local
65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
67 WREG32(mmIH_CNTL, ih_cntl); in iceland_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts() local
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in iceland_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in iceland_ih_irq_init() local
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); in iceland_ih_irq_init()
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); in iceland_ih_irq_init()
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H A Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts() local
65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
67 WREG32(mmIH_CNTL, ih_cntl); in cz_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts() local
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in cz_ih_disable_interrupts()
109 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cz_ih_irq_init() local
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); in cz_ih_irq_init()
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); in cz_ih_irq_init()
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H A Dsi_ih.c37 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts() local
40 ih_cntl |= ENABLE_INTR; in si_ih_enable_interrupts()
42 WREG32(IH_CNTL, ih_cntl); in si_ih_enable_interrupts()
50 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts() local
53 ih_cntl &= ~ENABLE_INTR; in si_ih_disable_interrupts()
55 WREG32(IH_CNTL, ih_cntl); in si_ih_disable_interrupts()
66 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_ih_irq_init() local
90 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_ih_irq_init()
92 ih_cntl |= RPTR_REARM; in si_ih_irq_init()
93 WREG32(IH_CNTL, ih_cntl); in si_ih_irq_init()
H A Dcik_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts() local
65 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; in cik_ih_enable_interrupts()
67 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts() local
85 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; in cik_ih_disable_interrupts()
87 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_ih_irq_init() local
146 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | in cik_ih_irq_init()
151 ih_cntl |= IH_CNTL__RPTR_REARM_MASK; in cik_ih_irq_init()
152 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_irq_init()
H A Dnavi10_ih.c108 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local
113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); in force_update_wptr_for_self_int()
116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
140 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); in force_update_wptr_for_self_int()
H A Dih_v6_0.c96 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local
98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2); in force_update_wptr_for_self_int()
101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl); in force_update_wptr_for_self_int()
H A Dih_v6_1.c96 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local
98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2); in force_update_wptr_for_self_int()
101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl); in force_update_wptr_for_self_int()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dr600.c3592 u32 ih_cntl = RREG32(IH_CNTL); in r600_enable_interrupts() local
3595 ih_cntl |= ENABLE_INTR; in r600_enable_interrupts()
3597 WREG32(IH_CNTL, ih_cntl); in r600_enable_interrupts()
3605 u32 ih_cntl = RREG32(IH_CNTL); in r600_disable_interrupts() local
3608 ih_cntl &= ~ENABLE_INTR; in r600_disable_interrupts()
3610 WREG32(IH_CNTL, ih_cntl); in r600_disable_interrupts()
3675 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in r600_irq_init() local
3728 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); in r600_irq_init()
3731 ih_cntl |= RPTR_REARM; in r600_irq_init()
3732 WREG32(IH_CNTL, ih_cntl); in r600_irq_init()
H A Dsi.c5921 u32 ih_cntl = RREG32(IH_CNTL); in si_enable_interrupts() local
5924 ih_cntl |= ENABLE_INTR; in si_enable_interrupts()
5926 WREG32(IH_CNTL, ih_cntl); in si_enable_interrupts()
5934 u32 ih_cntl = RREG32(IH_CNTL); in si_disable_interrupts() local
5937 ih_cntl &= ~ENABLE_INTR; in si_disable_interrupts()
5939 WREG32(IH_CNTL, ih_cntl); in si_disable_interrupts()
5981 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_irq_init() local
6031 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_irq_init()
6034 ih_cntl |= RPTR_REARM; in si_irq_init()
6035 WREG32(IH_CNTL, ih_cntl); in si_irq_init()
H A Dcik.c6814 u32 ih_cntl = RREG32(IH_CNTL); in cik_enable_interrupts() local
6817 ih_cntl |= ENABLE_INTR; in cik_enable_interrupts()
6819 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
6834 u32 ih_cntl = RREG32(IH_CNTL); in cik_disable_interrupts() local
6837 ih_cntl &= ~ENABLE_INTR; in cik_disable_interrupts()
6839 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
6939 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_irq_init() local
6989 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in cik_irq_init()
6992 ih_cntl |= RPTR_REARM; in cik_irq_init()
6993 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()