| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 218 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn301_smu_set_display_idle_optimization() argument
222 DC_LOG_DEBUG("%s(%x)\n", __func__, idle_info); in dcn301_smu_set_display_idle_optimization()
227 idle_info); in dcn301_smu_set_display_idle_optimization()
232 union display_idle_optimization_u idle_info = { 0 }; in dcn301_smu_enable_phy_refclk_pwrdwn() local
235 idle_info.idle_info.df_request_disabled = 1; in dcn301_smu_enable_phy_refclk_pwrdwn()
236 idle_info.idle_info.phy_ref_clk_off = 1; in dcn301_smu_enable_phy_refclk_pwrdwn()
244 idle_info.data); in dcn301_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn301_smu.h | 145 struct display_idle_optimization idle_info; member
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| H A D | vg_clk_mgr.c | 121 union display_idle_optimization_u idle_info = { 0 }; in vg_update_clocks() local
123 idle_info.idle_info.df_request_disabled = 1; in vg_update_clocks()
124 idle_info.idle_info.phy_ref_clk_off = 1; in vg_update_clocks()
126 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
134 union display_idle_optimization_u idle_info = { 0 }; in vg_update_clocks() local
136 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 232 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn316_smu_set_display_idle_optimization() argument
244 idle_info); in dcn316_smu_set_display_idle_optimization()
249 union display_idle_optimization_u idle_info = { 0 }; in dcn316_smu_enable_phy_refclk_pwrdwn() local
255 idle_info.idle_info.df_request_disabled = 1; in dcn316_smu_enable_phy_refclk_pwrdwn()
256 idle_info.idle_info.phy_ref_clk_off = 1; in dcn316_smu_enable_phy_refclk_pwrdwn()
262 idle_info.data); in dcn316_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn316_clk_mgr.c | 166 union display_idle_optimization_u idle_info = { 0 }; in dcn316_update_clocks() local
167 idle_info.idle_info.df_request_disabled = 1; in dcn316_update_clocks()
168 idle_info.idle_info.phy_ref_clk_off = 1; in dcn316_update_clocks()
169 idle_info.idle_info.s0i2_rdy = 1; in dcn316_update_clocks()
170 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
183 union display_idle_optimization_u idle_info = { 0 }; in dcn316_update_clocks() local
184 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
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| H A D | dcn316_smu.h | 118 struct display_idle_optimization idle_info; member
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 245 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn31_smu_set_display_idle_optimization() argument
257 idle_info); in dcn31_smu_set_display_idle_optimization()
262 union display_idle_optimization_u idle_info = { 0 }; in dcn31_smu_enable_phy_refclk_pwrdwn() local
268 idle_info.idle_info.df_request_disabled = 1; in dcn31_smu_enable_phy_refclk_pwrdwn()
269 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_smu_enable_phy_refclk_pwrdwn()
275 idle_info.data); in dcn31_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn31_clk_mgr.c | 170 union display_idle_optimization_u idle_info = { 0 }; in dcn31_update_clocks() local
171 idle_info.idle_info.df_request_disabled = 1; in dcn31_update_clocks()
172 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_update_clocks()
173 idle_info.idle_info.s0i2_rdy = 1; in dcn31_update_clocks()
174 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn31_update_clocks()
194 union display_idle_optimization_u idle_info = { 0 }; in dcn31_update_clocks() local
195 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn31_update_clocks()
642 union display_idle_optimization_u idle_info = { 0 }; in dcn31_set_low_power_state() local
644 idle_info.idle_info.df_request_disabled = 1; in dcn31_set_low_power_state()
645 idle_info.idle_info.phy_ref_clk_off = 1; in dcn31_set_low_power_state()
[all …]
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| H A D | dcn31_smu.h | 250 struct display_idle_optimization idle_info; member
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 258 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn315_smu_set_display_idle_optimization() argument
270 idle_info); in dcn315_smu_set_display_idle_optimization()
275 union display_idle_optimization_u idle_info = { 0 }; in dcn315_smu_enable_phy_refclk_pwrdwn() local
281 idle_info.idle_info.df_request_disabled = 1; in dcn315_smu_enable_phy_refclk_pwrdwn()
282 idle_info.idle_info.phy_ref_clk_off = 1; in dcn315_smu_enable_phy_refclk_pwrdwn()
288 idle_info.data); in dcn315_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn315_clk_mgr.c | 157 union display_idle_optimization_u idle_info = { 0 }; in dcn315_update_clocks() local
158 idle_info.idle_info.df_request_disabled = 1; in dcn315_update_clocks()
159 idle_info.idle_info.phy_ref_clk_off = 1; in dcn315_update_clocks()
160 idle_info.idle_info.s0i2_rdy = 1; in dcn315_update_clocks()
161 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
173 union display_idle_optimization_u idle_info = { 0 }; in dcn315_update_clocks() local
174 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
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| H A D | dcn315_smu.h | 110 struct display_idle_optimization idle_info; member
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 265 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn314_smu_set_display_idle_optimization() argument
277 idle_info); in dcn314_smu_set_display_idle_optimization()
282 union display_idle_optimization_u idle_info = { 0 }; in dcn314_smu_enable_phy_refclk_pwrdwn() local
288 idle_info.idle_info.df_request_disabled = 1; in dcn314_smu_enable_phy_refclk_pwrdwn()
289 idle_info.idle_info.phy_ref_clk_off = 1; in dcn314_smu_enable_phy_refclk_pwrdwn()
295 idle_info.data); in dcn314_smu_enable_phy_refclk_pwrdwn()
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| H A D | dcn314_smu.h | 89 struct display_idle_optimization idle_info; member
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
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| H A D | dcn314_clk_mgr.c | 197 union display_idle_optimization_u idle_info = { 0 }; in dcn314_update_clocks() local
198 idle_info.idle_info.df_request_disabled = 1; in dcn314_update_clocks()
199 idle_info.idle_info.phy_ref_clk_off = 1; in dcn314_update_clocks()
200 idle_info.idle_info.s0i2_rdy = 1; in dcn314_update_clocks()
201 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn314_update_clocks()
221 union display_idle_optimization_u idle_info = { 0 }; in dcn314_update_clocks() local
223 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn314_update_clocks()
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