| /openbmc/u-boot/drivers/i2c/ |
| H A D | davinci_i2c.c | 34 REG(&(i2c_base->i2c_con)) = 0;\
39 static int _wait_for_bus(struct i2c_regs *i2c_base) in _wait_for_bus() argument
43 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
46 stat = REG(&(i2c_base->i2c_stat)); in _wait_for_bus()
48 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
52 REG(&(i2c_base->i2c_stat)) = stat; in _wait_for_bus()
56 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
60 static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask) in _poll_i2c_irq() argument
66 stat = REG(&(i2c_base->i2c_stat)); in _poll_i2c_irq()
71 REG(&(i2c_base->i2c_stat)) = 0xffff; in _poll_i2c_irq()
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| H A D | designware_i2c.c | 41 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) in dw_i2c_enable() argument
45 writel(ena, &i2c_base->ic_enable); in dw_i2c_enable()
50 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) in dw_i2c_enable() argument
56 writel(ena, &i2c_base->ic_enable); in dw_i2c_enable()
57 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) in dw_i2c_enable()
79 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, in __dw_i2c_set_bus_speed() argument
95 dw_i2c_enable(i2c_base, false); in __dw_i2c_set_bus_speed()
97 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); in __dw_i2c_set_bus_speed()
110 writel(hcnt, &i2c_base->ic_hs_scl_hcnt); in __dw_i2c_set_bus_speed()
111 writel(lcnt, &i2c_base->ic_hs_scl_lcnt); in __dw_i2c_set_bus_speed()
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| H A D | omap24xx_i2c.c | 220 static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay) in wait_for_bb() argument
230 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); in wait_for_bb()
232 while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) & in wait_for_bb()
234 omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG); in wait_for_bb()
244 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); in wait_for_bb()
252 static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay) in wait_for_event() argument
262 status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg); in wait_for_event()
275 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); in wait_for_event()
282 static void flush_fifo(void __iomem *i2c_base, int ip_rev) in flush_fifo() argument
291 stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG); in flush_fifo()
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| H A D | fsl_i2c.c | 40 static const struct fsl_i2c_base *i2c_base[4] = { variable
499 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd, in fsl_i2c_init()
505 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); in fsl_i2c_probe_chip()
513 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], in fsl_i2c_read()
522 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], in fsl_i2c_write()
528 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, in fsl_i2c_set_bus_speed()
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| /openbmc/u-boot/board/samsung/arndale/ |
| H A D | arndale_spl.c | 36 .i2c_base = 0x12c60000,
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| /openbmc/u-boot/board/samsung/smdk5250/ |
| H A D | smdk5250_spl.c | 38 .i2c_base = 0x12c60000,
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| /openbmc/u-boot/board/samsung/smdk5420/ |
| H A D | smdk5420_spl.c | 38 .i2c_base = 0x12c60000,
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | spl.h | 55 u32 i2c_base; /* i2c base address */ member
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