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Searched refs:henvcfg (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/arch/riscv/kvm/
H A Dvcpu.c498 u64 henvcfg = 0; in kvm_riscv_vcpu_update_config() local
501 henvcfg |= ENVCFG_PBMTE; in kvm_riscv_vcpu_update_config()
504 henvcfg |= ENVCFG_STCE; in kvm_riscv_vcpu_update_config()
507 henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); in kvm_riscv_vcpu_update_config()
510 henvcfg |= ENVCFG_CBZE; in kvm_riscv_vcpu_update_config()
512 csr_write(CSR_HENVCFG, henvcfg); in kvm_riscv_vcpu_update_config()
514 csr_write(CSR_HENVCFGH, henvcfg >> 32); in kvm_riscv_vcpu_update_config()
/openbmc/qemu/target/riscv/
H A Dcpu_helper.c84 return env->henvcfg & HENVCFG_LPE; in cpu_get_fcfien()
113 return env->henvcfg & HENVCFG_SSE; in cpu_get_bcfien()
626 get_field(env->henvcfg, HENVCFG_LPE)) { in riscv_cpu_swap_hypervisor_regs()
1004 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); in get_physical_address()
1005 adue = adue && (env->henvcfg & HENVCFG_ADUE); in get_physical_address()
H A Dmachine.c309 VMSTATE_UINT64(env.henvcfg, RISCVCPU),
H A Dcsr.c498 get_field(env->henvcfg, HENVCFG_STCE))) { in sstc()
2457 (env->virt_enabled ? get_field(env->henvcfg, HENVCFG_SSE) : true)) { in write_senvcfg()
2480 *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | in read_henvcfg()
2510 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); in write_henvcfg()
2525 *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | in read_henvcfgh()
2543 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); in write_henvcfgh()
H A Dop_helper.c143 (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || in check_zicbo_envcfg()
H A Dcpu.h468 uint64_t henvcfg; member
H A Dcpu.c972 env->henvcfg = 0; in riscv_cpu_reset_hold()