Searched refs:henvcfg (Results 1 – 7 of 7) sorted by relevance
476 u64 henvcfg = 0; in kvm_riscv_vcpu_update_config() local479 henvcfg |= ENVCFG_PBMTE; in kvm_riscv_vcpu_update_config()482 henvcfg |= ENVCFG_STCE; in kvm_riscv_vcpu_update_config()485 henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); in kvm_riscv_vcpu_update_config()488 henvcfg |= ENVCFG_CBZE; in kvm_riscv_vcpu_update_config()490 csr_write(CSR_HENVCFG, henvcfg); in kvm_riscv_vcpu_update_config()492 csr_write(CSR_HENVCFGH, henvcfg >> 32); in kvm_riscv_vcpu_update_config()
83 return env->henvcfg & HENVCFG_LPE; in cpu_get_fcfien()112 return env->henvcfg & HENVCFG_SSE; in cpu_get_bcfien()625 get_field(env->henvcfg, HENVCFG_LPE)) { in riscv_cpu_swap_hypervisor_regs()1003 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); in get_physical_address()1004 adue = adue && (env->henvcfg & HENVCFG_ADUE); in get_physical_address()
309 VMSTATE_UINT64(env.henvcfg, RISCVCPU),
493 get_field(env->henvcfg, HENVCFG_STCE))) { in sstc()2452 (env->virt_enabled ? get_field(env->henvcfg, HENVCFG_SSE) : true)) { in write_senvcfg()2475 *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | in read_henvcfg()2505 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); in write_henvcfg()2520 *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | in read_henvcfgh()2538 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); in write_henvcfgh()
143 (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || in check_zicbo_envcfg()
468 uint64_t henvcfg; member
972 env->henvcfg = 0; in riscv_cpu_reset_hold()