1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> 4 * 5 */ 6 7 #ifndef _RESET_MANAGER_S10_ 8 #define _RESET_MANAGER_S10_ 9 10 void reset_cpu(ulong addr); 11 void reset_deassert_peripherals_handoff(void); 12 13 void socfpga_bridges_reset(int enable); 14 15 void socfpga_per_reset(u32 reset, int set); 16 void socfpga_per_reset_all(void); 17 18 struct socfpga_reset_manager { 19 u32 status; 20 u32 mpu_rst_stat; 21 u32 misc_stat; 22 u32 padding1; 23 u32 hdsk_en; 24 u32 hdsk_req; 25 u32 hdsk_ack; 26 u32 hdsk_stall; 27 u32 mpumodrst; 28 u32 per0modrst; 29 u32 per1modrst; 30 u32 brgmodrst; 31 u32 padding2; 32 u32 cold_mod_reset; 33 u32 padding3; 34 u32 dbg_mod_reset; 35 u32 tap_mod_reset; 36 u32 padding4; 37 u32 padding5; 38 u32 brg_warm_mask; 39 u32 padding6[3]; 40 u32 tst_stat; 41 u32 padding7; 42 u32 hdsk_timeout; 43 u32 mpul2flushtimeout; 44 u32 dbghdsktimeout; 45 }; 46 47 #define RSTMGR_MPUMODRST_CORE0 0 48 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 49 #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 50 51 /* 52 * Define a reset identifier, from which a permodrst bank ID 53 * and reset ID can be extracted using the subsequent macros 54 * RSTMGR_RESET() and RSTMGR_BANK(). 55 */ 56 #define RSTMGR_BANK_OFFSET 8 57 #define RSTMGR_BANK_MASK 0x7 58 #define RSTMGR_RESET_OFFSET 0 59 #define RSTMGR_RESET_MASK 0x1f 60 #define RSTMGR_DEFINE(_bank, _offset) \ 61 ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) 62 63 /* Extract reset ID from the reset identifier. */ 64 #define RSTMGR_RESET(_reset) \ 65 (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) 66 67 /* Extract bank ID from the reset identifier. */ 68 #define RSTMGR_BANK(_reset) \ 69 (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) 70 71 /* 72 * SocFPGA Stratix10 reset IDs, bank mapping is as follows: 73 * 0 ... mpumodrst 74 * 1 ... per0modrst 75 * 2 ... per1modrst 76 * 3 ... brgmodrst 77 */ 78 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 79 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 80 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) 81 #define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) 82 #define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) 83 #define RSTMGR_NAND RSTMGR_DEFINE(1, 5) 84 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) 85 #define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) 86 #define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) 87 #define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) 88 #define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) 89 #define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) 90 #define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) 91 #define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) 92 #define RSTMGR_DMA RSTMGR_DEFINE(1, 16) 93 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) 94 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) 95 #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) 96 #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) 97 #define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) 98 #define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) 99 #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) 100 #define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) 101 #define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) 102 #define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) 103 #define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) 104 #define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) 105 #define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) 106 #define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) 107 #define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) 108 #define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) 109 #define RSTMGR_SDR RSTMGR_DEFINE(3, 6) 110 111 /* Create a human-readable reference to SoCFPGA reset. */ 112 #define SOCFPGA_RESET(_name) RSTMGR_##_name 113 114 #endif /* _RESET_MANAGER_S10_ */ 115