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Searched refs:harts (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Dboot.c37 bool riscv_is_32bit(RISCVHartArrayState *harts) in riscv_is_32bit() argument
39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); in riscv_is_32bit()
70 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, in riscv_calc_kernel_start_addr() argument
72 if (riscv_is_32bit(harts)) { in riscv_calc_kernel_start_addr()
79 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) in riscv_default_firmware_name() argument
81 if (riscv_is_32bit(harts)) { in riscv_default_firmware_name()
219 RISCVHartArrayState *harts, in riscv_load_kernel() argument
263 if (riscv_is_32bit(harts)) { in riscv_load_kernel()
347 RISCVHartArrayState *harts, in riscv_rom_copy_firmware_info() argument
356 if (riscv_is_32bit(harts)) { in riscv_rom_copy_firmware_info()
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H A Driscv_hart.c48 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); in riscv_hart_realize()
49 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); in riscv_hart_realize()
50 s->harts[idx].env.mhartid = s->hartid_base + idx; in riscv_hart_realize()
51 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); in riscv_hart_realize()
52 return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); in riscv_hart_realize()
60 s->harts = g_new0(RISCVCPU, s->num_harts); in riscv_harts_realize()
H A Dspike.c116 riscv_isa_write_fdt(&s->soc[socket].harts[cpu], fdt, cpu_name); in create_fdt()
H A Dsifive_u.c181 riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename); in create_fdt()
183 riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); in create_fdt()
H A Dvirt-acpi-build.c256 RISCVCPU *cpu = &s->soc[0].harts[0]; in build_rhct()
H A Dvirt.c231 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; in create_fdt_socket_cpus()
718 RISCVCPU hart = s->soc[0].harts[0]; in create_fdt_pmu()
/openbmc/qemu/include/hw/riscv/
H A Dboot.h30 bool riscv_is_32bit(RISCVHartArrayState *harts);
34 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
40 const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
47 RISCVHartArrayState *harts,
54 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
60 RISCVHartArrayState *harts,
H A Driscv_hart.h41 RISCVCPU *harts; member
/openbmc/linux/Documentation/riscv/
H A Dboot.rst68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
69 wins a lottery and executes the early boot code while the other harts are
73 initialization phase and then will start all other harts using the SBI HSM